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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2014-09-29 01:37:59 +0900
committerTom Rini <trini@ti.com>2014-10-10 09:44:43 -0400
commit9ed3246e19a42392bf0fd676dcbbe3539cc46ec1 (patch)
treec0ac8faaf0337e8a701f188db5a2033b3d98e1aa /arch/powerpc/cpu/ppc4xx
parent1521cdc5303db2a3ec5a09231fbaa5831561bf71 (diff)
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powerpc: ppc4xx: remove board support for bluestone
This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx')
-rw-r--r--arch/powerpc/cpu/ppc4xx/Kconfig4
-rw-r--r--arch/powerpc/cpu/ppc4xx/cpu.c14
-rw-r--r--arch/powerpc/cpu/ppc4xx/cpu_init.c4
-rw-r--r--arch/powerpc/cpu/ppc4xx/speed.c75
-rw-r--r--arch/powerpc/cpu/ppc4xx/start.S8
5 files changed, 6 insertions, 99 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index d525ad3..56abe8d 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -52,9 +52,6 @@ config TARGET_ACADIA
config TARGET_BAMBOO
bool "Support bamboo"
-config TARGET_BLUESTONE
- bool "Support bluestone"
-
config TARGET_BUBINGA
bool "Support bubinga"
@@ -239,7 +236,6 @@ endchoice
source "board/amcc/acadia/Kconfig"
source "board/amcc/bamboo/Kconfig"
-source "board/amcc/bluestone/Kconfig"
source "board/amcc/bubinga/Kconfig"
source "board/amcc/canyonlands/Kconfig"
source "board/amcc/ebony/Kconfig"
diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 6a48526..aab65d4 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -234,20 +234,6 @@ static char *bootstrap_str[] = {
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif
-#if defined(CONFIG_APM821XX)
-#define SDR0_PINSTP_SHIFT 29
-static char *bootstrap_str[] = {
- "RESERVED",
- "RESERVED",
- "RESERVED",
- "NAND (8 bits)",
- "NOR (8 bits)",
- "NOR (8 bits) w/PLL Bypassed",
- "I2C (Addr 0x54)",
- "I2C (Addr 0x52)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
-#endif
#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 0b27d29..2256123 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -284,7 +284,7 @@ cpu_init_f (void)
reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
- !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
+ !defined(CONFIG_SYS_4xx_GPIO_TABLE)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
@@ -440,7 +440,7 @@ cpu_init_f (void)
#if defined(CONFIG_405EX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+ defined(CONFIG_460SX)
/*
* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
*/
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 4baee77..3e1a701 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -171,7 +171,7 @@ ulong get_PCI_freq (void)
#elif defined(CONFIG_440)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+ defined(CONFIG_460SX)
static u8 pll_fwdv_multi_bits[] = {
/* values for: 1 - 16 */
0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@@ -232,78 +232,6 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
return 0;
}
-#if defined(CONFIG_APM821XX)
-
-void get_sys_info(sys_info_t *sysInfo)
-{
- unsigned long plld;
- unsigned long temp;
- unsigned long mul;
- unsigned long cpudv;
- unsigned long plb2dv;
- unsigned long ddr2dv;
-
- /* Calculate Forward divisor A and Feeback divisor */
- mfcpr(CPR0_PLLD, plld);
-
- temp = CPR0_PLLD_FWDVA(plld);
- sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
-
- temp = CPR0_PLLD_FDV(plld);
- sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
-
- /* Calculate OPB clock divisor */
- mfcpr(CPR0_OPBD, temp);
- temp = CPR0_OPBD_OPBDV(temp);
- sysInfo->pllOpbDiv = temp ? temp : 4;
-
- /* Calculate Peripheral clock divisor */
- mfcpr(CPR0_PERD, temp);
- temp = CPR0_PERD_PERDV(temp);
- sysInfo->pllExtBusDiv = temp ? temp : 4;
-
- /* Calculate CPU clock divisor */
- mfcpr(CPR0_CPUD, temp);
- temp = CPR0_CPUD_CPUDV(temp);
- cpudv = temp ? temp : 8;
-
- /* Calculate PLB2 clock divisor */
- mfcpr(CPR0_PLB2D, temp);
- temp = CPR0_PLB2D_PLB2DV(temp);
- plb2dv = temp ? temp : 4;
-
- /* Calculate DDR2 clock divisor */
- mfcpr(CPR0_DDR2D, temp);
- temp = CPR0_DDR2D_DDR2DV(temp);
- ddr2dv = temp ? temp : 4;
-
- /* Calculate 'M' based on feedback source */
- mfcpr(CPR0_PLLC, temp);
- temp = CPR0_PLLC_SEL(temp);
- if (temp == 0) {
- /* PLL internal feedback */
- mul = sysInfo->pllFbkDiv;
- } else {
- /* PLL PerClk feedback */
- mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv
- * plb2dv * 2 * sysInfo->pllOpbDiv *
- sysInfo->pllExtBusDiv;
- }
-
- /* Now calculate the individual clocks */
- sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1);
- sysInfo->freqProcessor = sysInfo->freqVCOMhz /
- sysInfo->pllFwdDivA / cpudv;
- sysInfo->freqPLB = sysInfo->freqVCOMhz /
- sysInfo->pllFwdDivA / cpudv / plb2dv / 2;
- sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
- sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
- sysInfo->freqDDR = sysInfo->freqVCOMhz /
- sysInfo->pllFwdDivA / cpudv / ddr2dv / 2;
- sysInfo->freqUART = sysInfo->freqPLB;
-}
-
-#else
/*
* AMCC_TODO: verify this routine against latest EAS, cause stuff changed
* with latest EAS
@@ -361,7 +289,6 @@ void get_sys_info (sys_info_t * sysInfo)
return;
}
-#endif
#elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 11b55d5..09a02d7 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -664,8 +664,7 @@ _start:
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460SX)
mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_APM821XX)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
lis r1, 0x0000
ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
mtdcr L2_CACHE_CFG,r1
@@ -694,7 +693,7 @@ _start:
ori r1,r1, 0x0980 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
- defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
+ defined(CONFIG_460GT)
lis r1,0x0000 /* BAS = X_0000_0000 */
ori r1,r1,0x0984 /* first 64k */
mtdcr ISRAM0_SB0CR,r1
@@ -707,8 +706,7 @@ _start:
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
- defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
lis r2,0x7fff
ori r2,r2,0xffff
mfdcr r1,ISRAM1_DPC