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authorYork Sun <yorksun@freescale.com>2011-06-07 09:42:16 +0800
committerKumar Gala <galak@kernel.crashing.org>2011-07-11 13:24:20 -0500
commit1b3e3c4f263ff20b95c3514eefbde47e950c39e0 (patch)
tree4043fc4d718f49dee1a2d88daa1b9ef87b435980 /arch/powerpc/cpu/mpc8xxx/ddr/main.c
parentaeb6716a12c68644d6dc1e798b724086c3cfcd24 (diff)
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powerpc/mpc8xxx: Enable calculation for fixed DDR chips
We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx/ddr/main.c')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/main.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 62a73dd..3c49fa9 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -325,6 +325,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
switch (start_step) {
case STEP_GET_SPD:
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
/* STEP 1: Gather all DIMM SPD data */
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
@@ -356,6 +357,17 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
}
}
+#else
+ case STEP_COMPUTE_DIMM_PARMS:
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+ dimm_params_t *pdimm =
+ &(pinfo->dimm_params[i][j]);
+ fsl_ddr_get_dimm_params(pdimm, i, j);
+ }
+ }
+ debug("Filling dimm parameters from board specific file\n");
+#endif
case STEP_COMPUTE_COMMON_PARMS:
/*
* STEP 3: Compute a common set of timing parameters