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| author | John Schmoller <jschmoller@xes-inc.com> | 2011-03-10 16:09:26 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-03-13 11:24:44 -0500 |
| commit | cc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd (patch) | |
| tree | 1f6094113165e0f143b233f054416dbd67b68c9c /arch/powerpc/cpu/mpc86xx/interrupts.c | |
| parent | b71ea33699bb694964929e2cdced80ef794bde69 (diff) | |
| download | u-boot-imx-cc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd.zip u-boot-imx-cc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd.tar.gz u-boot-imx-cc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd.tar.bz2 | |
mpc8[5/6]xx: Ensure POST word does not get reset
The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors. When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word. To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc86xx/interrupts.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc86xx/interrupts.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc86xx/interrupts.c b/arch/powerpc/cpu/mpc86xx/interrupts.c index d8ad6d3..14821f4 100644 --- a/arch/powerpc/cpu/mpc86xx/interrupts.c +++ b/arch/powerpc/cpu/mpc86xx/interrupts.c @@ -35,12 +35,24 @@ #include <mpc86xx.h> #include <command.h> #include <asm/processor.h> +#ifdef CONFIG_POST +#include <post.h> +#endif int interrupt_init_cpu(unsigned long *decrementer_count) { volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_pic_t *pic = &immr->im_pic; +#ifdef CONFIG_POST + /* + * The POST word is stored in the PIC's TFRR register which gets + * cleared when the PIC is reset. Save it off so we can restore it + * later. + */ + ulong post_word = post_word_load(); +#endif + pic->gcr = MPC86xx_PICGCR_RST; while (pic->gcr & MPC86xx_PICGCR_RST) ; @@ -74,6 +86,10 @@ int interrupt_init_cpu(unsigned long *decrementer_count) pic->ctpr = 0; /* 40080 clear current task priority register */ #endif +#ifdef CONFIG_POST + post_word_store(post_word); +#endif + return 0; } |