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| author | Andy Fleming <afleming@freescale.com> | 2013-03-25 07:33:10 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-14 16:00:24 -0500 |
| commit | cd7ad629960bf53eb2d7247ce1d499770b316116 (patch) | |
| tree | 6d23da72e7bfba9f924498fff82eca94e03b6980 /arch/powerpc/cpu/mpc85xx | |
| parent | 0cb3325cd3a2f574c0ab73ab83b892c27cacab74 (diff) | |
| download | u-boot-imx-cd7ad629960bf53eb2d7247ce1d499770b316116.zip u-boot-imx-cd7ad629960bf53eb2d7247ce1d499770b316116.tar.gz u-boot-imx-cd7ad629960bf53eb2d7247ce1d499770b316116.tar.bz2 | |
powerpc/mpc85xx: Add definitions for HDBCR registers
Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually
use those definitions.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 8 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 5c4b1e3..0dea871 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -69,9 +69,9 @@ __secondary_start_page: #endif #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 - mfspr r3,977 + mfspr r3,SPRN_HDBCR1 oris r3,r3,0x0100 - mtspr 977,r3 + mtspr SPRN_HDBCR1,r3 #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 @@ -93,10 +93,10 @@ __secondary_start_page: 1: /* Erratum says set bits 55:60 to 001001 */ msync isync - mfspr r3,976 + mfspr r3,SPRN_HDBCR0 li r4,0x48 rlwimi r3,r4,0,0x1f8 - mtspr 976,r3 + mtspr SPRN_HDBCR0,r3 isync 2: #endif diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 3f76ee6..2ce5505 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -116,10 +116,10 @@ _start_e500: /* Erratum says set bits 55:60 to 001001 */ msync isync - mfspr r3,976 + mfspr r3,SPRN_HDBCR0 li r4,0x48 rlwimi r3,r4,0,0x1f8 - mtspr 976,r3 + mtspr SPRN_HDBCR0,r3 isync 2: #endif @@ -372,9 +372,9 @@ l2_disabled: #endif #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 - mfspr r3,977 + mfspr r3,SPRN_HDBCR1 oris r3,r3,0x0100 - mtspr 977,r3 + mtspr SPRN_HDBCR1,r3 #endif /* Enable Branch Prediction */ |