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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:31 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:33 -0500 |
| commit | 98ffa19053f2d10578a227de4e441698226fde0a (patch) | |
| tree | 36010ca075f6ce2e62902c4b6321eff04f8cd5b4 /arch/powerpc/cpu/mpc85xx/speed.c | |
| parent | ffd06e0231ac3fd0c5810f39f6e23527948df1c7 (diff) | |
| download | u-boot-imx-98ffa19053f2d10578a227de4e441698226fde0a.zip u-boot-imx-98ffa19053f2d10578a227de4e441698226fde0a.tar.gz u-boot-imx-98ffa19053f2d10578a227de4e441698226fde0a.tar.bz2 | |
powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform
New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/speed.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f07a28b..8a8f317 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -82,7 +82,11 @@ void get_sys_info (sys_info_t * sysInfo) uint mem_pll_rat; sysInfo->freqSystemBus = sysclk; +#ifdef CONFIG_DDR_CLK_FREQ + sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ; +#else sysInfo->freqDDRBus = sysclk; +#endif sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> |