From 98ffa19053f2d10578a227de4e441698226fde0a Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:31 +0000 Subject: powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform New corenet platforms with chassis2 have separated DDR clock inputs. Use CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of detecting and displaying synchronous vs asynchronous mode. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f07a28b..8a8f317 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -82,7 +82,11 @@ void get_sys_info (sys_info_t * sysInfo) uint mem_pll_rat; sysInfo->freqSystemBus = sysclk; +#ifdef CONFIG_DDR_CLK_FREQ + sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ; +#else sysInfo->freqDDRBus = sysclk; +#endif sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> -- cgit v1.1