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| author | Tom Rini <trini@ti.com> | 2013-05-14 18:47:43 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-05-15 08:41:04 -0400 |
| commit | fb651b10d43be36e7d7e16704c4b5ea1e295587a (patch) | |
| tree | b2f5450c8031935a92d0357cb677bac99d3be537 /arch/powerpc/cpu/mpc85xx/release.S | |
| parent | d6ed3222229974682799bd2083f2ceeac6f912b1 (diff) | |
| parent | f63d638dad5dd13f445d1e87ce824d4a7cd61f79 (diff) | |
| download | u-boot-imx-fb651b10d43be36e7d7e16704c4b5ea1e295587a.zip u-boot-imx-fb651b10d43be36e7d7e16704c4b5ea1e295587a.tar.gz u-boot-imx-fb651b10d43be36e7d7e16704c4b5ea1e295587a.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/release.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/release.S | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 5c4b1e3..467ea10 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -69,9 +69,9 @@ __secondary_start_page: #endif #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 - mfspr r3,977 + mfspr r3,SPRN_HDBCR1 oris r3,r3,0x0100 - mtspr 977,r3 + mtspr SPRN_HDBCR1,r3 #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 @@ -93,10 +93,10 @@ __secondary_start_page: 1: /* Erratum says set bits 55:60 to 001001 */ msync isync - mfspr r3,976 + mfspr r3,SPRN_HDBCR0 li r4,0x48 rlwimi r3,r4,0,0x1f8 - mtspr 976,r3 + mtspr SPRN_HDBCR0,r3 isync 2: #endif @@ -159,9 +159,9 @@ __secondary_start_page: * we cannot access it yet before setting up a new TLB */ mfspr r0,SPRN_PIR -#if defined(CONFIG_E6500) +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* - * PIR definition for E6500 + * PIR definition for Chassis 2 * 0-17 Reserved (logic 0s) * 8-19 CHIP_ID, 2'b00 - SoC 1 * all others - reserved @@ -187,7 +187,7 @@ __secondary_start_page: slwi r8,r4,6 /* spin table is padded to 64 byte */ add r10,r3,r8 -#ifdef CONFIG_E6500 +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 mfspr r0,SPRN_PIR /* * core 0 thread 0: pir reset value 0x00, new pir 0 |