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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2012-04-29 23:56:43 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-07-06 17:30:30 -0500 |
| commit | 689f00fc7e65d90222890c2ac4225137002db846 (patch) | |
| tree | 673f14faa6487948ca3062f9eed44ad40ffffa40 /arch/powerpc/cpu/mpc85xx/p4080_ids.c | |
| parent | 5344f7a258dfb74be11289367b0ffe4852ce74d3 (diff) | |
| download | u-boot-imx-689f00fc7e65d90222890c2ac4225137002db846.zip u-boot-imx-689f00fc7e65d90222890c2ac4225137002db846.tar.gz u-boot-imx-689f00fc7e65d90222890c2ac4225137002db846.tar.bz2 | |
powerpc/85xx:Make debug exception vector accessible
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.
1) While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction from the debug exception vector (IVPR + IVOR15); since now
we are in AS=0, the application needs to ensure the proper TLB configuration to
have (IVOR + IVOR15) accessible from AS=0 also.
Create a temporary TLB in AS0 to make sure debug exception verctor is
accessible on debug exception.
2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/p4080_ids.c')
0 files changed, 0 insertions, 0 deletions