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| author | York Sun <yorksun@freescale.com> | 2014-05-23 13:15:00 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-06-05 13:45:07 -0700 |
| commit | 9855b3beca648dabe4d86b06d36bf219ebd0732d (patch) | |
| tree | c0a02085628640beec9e0d69f31af84f00eabb8e /arch/powerpc/cpu/mpc85xx/p1010_serdes.c | |
| parent | aaee5230f135bbfbe7abe6388cd04931f322db68 (diff) | |
| download | u-boot-imx-9855b3beca648dabe4d86b06d36bf219ebd0732d.zip u-boot-imx-9855b3beca648dabe4d86b06d36bf219ebd0732d.tar.gz u-boot-imx-9855b3beca648dabe4d86b06d36bf219ebd0732d.tar.bz2 | |
powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/p1010_serdes.c')
0 files changed, 0 insertions, 0 deletions