summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu/mpc83xx/cpu.c
diff options
context:
space:
mode:
authorBecky Bruce <beckyb@kernel.crashing.org>2010-06-17 11:37:20 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-07-16 10:55:09 -0500
commitf51cdaf19141151ce2b40d562a468605340f2315 (patch)
tree60b51af79796f061d119f2839d101f9584964dfc /arch/powerpc/cpu/mpc83xx/cpu.c
parent0914f4832887341ee073d2d2bfbada69a6872548 (diff)
downloadu-boot-imx-f51cdaf19141151ce2b40d562a468605340f2315.zip
u-boot-imx-f51cdaf19141151ce2b40d562a468605340f2315.tar.gz
u-boot-imx-f51cdaf19141151ce2b40d562a468605340f2315.tar.bz2
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc83xx/cpu.c')
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 42387b4..86a24fd 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -157,16 +157,16 @@ int checkcpu(void)
void upmconfig (uint upm, uint *table, uint size)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbus = &immap->lbus;
+ volatile fsl_lbc_t *lbc = &immap->im_lbc;
volatile uchar *dummy = NULL;
const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
- volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
+ volatile u32 *mxmr = &lbc->mamr + upm; /* ptr to mamr, mbmr, or mcmr */
uint i;
- /* Scan all the banks to determine the base address of the device */
+ /* Find the address for the dummy write transaction */
for (i = 0; i < 8; i++) {
- if ((lbus->bank[i].br & BR_MSEL) == msel) {
- dummy = (uchar *) (lbus->bank[i].br & BR_BA);
+ if ((get_lbc_br(i) & BR_MSEL) == msel) {
+ dummy = (uchar *) (get_lbc_br(i) & BR_BA);
break;
}
}
@@ -180,7 +180,7 @@ void upmconfig (uint upm, uint *table, uint size)
*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
for (i = 0; i < size; i++) {
- lbus->mdr = table[i];
+ lbc->mdr = table[i];
__asm__ __volatile__ ("sync");
*dummy = 0; /* Write the value to memory and increment MAD */
__asm__ __volatile__ ("sync");