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author | Akshay Saraswat <akshay.s@samsung.com> | 2015-02-20 13:27:15 +0530 |
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committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-02-28 18:03:46 +0900 |
commit | 67a0652c47ec568ea274f5ff0303c9bba8ceddbf (patch) | |
tree | 5e5324b6a3bf55684f0c2a8de4c129d95fb4c714 /arch/nios2/include/asm/nios2.h | |
parent | a389531439a7d5cea2829054edcf438dc76e79a9 (diff) | |
download | u-boot-imx-67a0652c47ec568ea274f5ff0303c9bba8ceddbf.zip u-boot-imx-67a0652c47ec568ea274f5ff0303c9bba8ceddbf.tar.gz u-boot-imx-67a0652c47ec568ea274f5ff0303c9bba8ceddbf.tar.bz2 |
Exynos542x: Add workaround for exynos iROM errata
iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping to wrong address and create undesired results.
Logic of the workaround:
Step-1: iROM code checks value at address 0x2020028.
Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
else, it continues executing normally.
Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
0x2020028 and jump address (pointer to function low_power_start)
in (0x202000+CPUid*4).
Step-4: When secondary cores recieve event signal they jump to this address
and continue execution.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/nios2/include/asm/nios2.h')
0 files changed, 0 insertions, 0 deletions