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authorPaul Burton <paul.burton@imgtec.com>2016-09-21 11:18:58 +0100
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-09-21 15:04:04 +0200
commitd608254b0aa23607df1dcb5a7ca07de9a8ec9bb0 (patch)
tree08974b3c02079cc147794c9a28eab7f35e0cd156 /arch/mips
parentc5b8412d60e22b49348a63848cbf7b6ab5ccb16e (diff)
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MIPS: Clear hazard between TagLo writes & cache ops
Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache instructions execute. Ensure that hazard is cleared by inserting an ehb instruction between the TagLo writes & cache op loop. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/lib/cache_init.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index e61432e..53e903a 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -293,6 +293,7 @@ l2_init:
l1_init:
mtc0 zero, CP0_TAGLO
mtc0 zero, CP0_TAGLO, 2
+ ehb
/*
* The caches are probably in an indeterminate state, so we force good