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author | Purna Chandra Mandal <purna.mandal@microchip.com> | 2016-01-28 15:30:10 +0530 |
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committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-02-01 22:14:00 +0100 |
commit | 32c1a6eef8b467bb776f989caf0480fce6218598 (patch) | |
tree | ab99b876e738a8211d3c391df8aae8ddd7138d93 /arch/mips/mach-pic32/include/mach/pic32.h | |
parent | 91ec615e5474e38bbd65f36b861849e70311548b (diff) | |
download | u-boot-imx-32c1a6eef8b467bb776f989caf0480fce6218598.zip u-boot-imx-32c1a6eef8b467bb776f989caf0480fce6218598.tar.gz u-boot-imx-32c1a6eef8b467bb776f989caf0480fce6218598.tar.bz2 |
MIPS: initial infrastructure for Microchip PIC32 architecture
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/mips/mach-pic32/include/mach/pic32.h')
-rw-r--r-- | arch/mips/mach-pic32/include/mach/pic32.h | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/arch/mips/mach-pic32/include/mach/pic32.h b/arch/mips/mach-pic32/include/mach/pic32.h new file mode 100644 index 0000000..7e41810 --- /dev/null +++ b/arch/mips/mach-pic32/include/mach/pic32.h @@ -0,0 +1,76 @@ +/* + * (c) 2015 Paul Thacker <paul.thacker@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __PIC32_REGS_H__ +#define __PIC32_REGS_H__ + +#include <asm/io.h> + +/* System Configuration */ +#define PIC32_CFG_BASE 0x1f800000 + +/* System config register offsets */ +#define CFGCON 0x0000 +#define DEVID 0x0020 +#define SYSKEY 0x0030 +#define PMD1 0x0040 +#define PMD7 0x00a0 +#define CFGEBIA 0x00c0 +#define CFGEBIC 0x00d0 +#define CFGPG 0x00e0 +#define CFGMPLL 0x0100 + +/* Non Volatile Memory (NOR flash) */ +#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600) +/* Oscillator Configuration */ +#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200) +/* Peripheral Pin Select Input */ +#define PPS_IN_BASE 0x1f801400 +/* Peripheral Pin Select Output */ +#define PPS_OUT_BASE 0x1f801500 +/* Pin Config */ +#define PINCTRL_BASE 0x1f860000 + +/* USB Core */ +#define PIC32_USB_CORE_BASE 0x1f8e3000 +#define PIC32_USB_CTRL_BASE 0x1f884000 + +/* SPI1-SPI6 */ +#define PIC32_SPI1_BASE 0x1f821000 + +/* Prefetch Module */ +#define PREFETCH_BASE 0x1f8e0000 + +/* DDR2 Controller */ +#define PIC32_DDR2C_BASE 0x1f8e8000 + +/* DDR2 PHY */ +#define PIC32_DDR2P_BASE 0x1f8e9100 + +/* EBI */ +#define PIC32_EBI_BASE 0x1f8e1000 + +/* SQI */ +#define PIC32_SQI_BASE 0x1f8e2000 + +struct pic32_reg_atomic { + u32 raw; + u32 clr; + u32 set; + u32 inv; +}; + +#define _CLR_OFFSET 0x04 +#define _SET_OFFSET 0x08 +#define _INV_OFFSET 0x0c + +static inline void __iomem *pic32_get_syscfg_base(void) +{ + return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE); +} + +#endif /* __PIC32_REGS_H__ */ |