diff options
| author | Wills Wang <wills.wang@live.com> | 2016-04-12 11:09:20 +0800 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-05-21 01:36:38 +0200 |
| commit | 5691d10a0166d5a324f96d98757f206c6dedc989 (patch) | |
| tree | 452ece4bdca51adbd4fc3217585a1b6353aea756 /arch/mips/mach-ath79 | |
| parent | 773f3b25384363d53e457f1faae77c91db76e0c4 (diff) | |
| download | u-boot-imx-5691d10a0166d5a324f96d98757f206c6dedc989.zip u-boot-imx-5691d10a0166d5a324f96d98757f206c6dedc989.tar.gz u-boot-imx-5691d10a0166d5a324f96d98757f206c6dedc989.tar.bz2 | |
ath79: ar933x: use BIT macro for bit shift operation
used a uniform BIT macro for register bit-field shift
Signed-off-by: Wills Wang <wills.wang@live.com>
Diffstat (limited to 'arch/mips/mach-ath79')
| -rw-r--r-- | arch/mips/mach-ath79/ar933x/ddr.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c index 74e8e80..91452bc 100644 --- a/arch/mips/mach-ath79/ar933x/ddr.c +++ b/arch/mips/mach-ath79/ar933x/ddr.c @@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; #define DDR_CTRL_UPD_EMRS BIT(1) #define DDR_CTRL_UPD_MRS BIT(0) -#define DDR_REFRESH_EN (1 << 14) +#define DDR_REFRESH_EN BIT(14) #define DDR_REFRESH_M 0x3ff #define DDR_REFRESH(x) ((x) & 0x3ff) #define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390)) @@ -48,7 +48,7 @@ DECLARE_GLOBAL_DATA_PTR; #define DDR_CAS_L_M 0x17 #define DDR_CAS_L_S 27 #define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S) -#define DDR_OPEN (1 << 30) +#define DDR_OPEN BIT(30) #define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \ DDR_TRP(6) | DDR_TRRD(4) | \ DDR_TRFC(30) | DDR_TMRD(15) | \ @@ -57,10 +57,10 @@ DECLARE_GLOBAL_DATA_PTR; #define DDR_BURST_LEN_S 0 #define DDR_BURST_LEN_M 0xf #define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S) -#define DDR_BURST_TYPE (1 << 4) -#define DDR_CNTL_OE_EN (1 << 5) -#define DDR_PHASE_SEL (1 << 6) -#define DDR_CKE (1 << 7) +#define DDR_BURST_TYPE BIT(4) +#define DDR_CNTL_OE_EN BIT(5) +#define DDR_PHASE_SEL BIT(6) +#define DDR_CKE BIT(7) #define DDR_TWR_S 8 #define DDR_TWR_M 0xf #define DDR_TWR(x) ((x) << DDR_TWR_S) @@ -76,7 +76,7 @@ DECLARE_GLOBAL_DATA_PTR; #define DDR_G_OPEN_L_S 26 #define DDR_G_OPEN_L_M 0xf #define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S) -#define DDR_HALF_WIDTH_LOW (1 << 31) +#define DDR_HALF_WIDTH_LOW BIT(31) #define DDR_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \ DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \ DDR_TRTP(8) | DDR_TWTR(14) | \ |