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| author | Stefano Babic <sbabic@denx.de> | 2016-05-24 14:55:06 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-05-24 14:55:06 +0200 |
| commit | 08ca213acadef61748dc62d48b0f5c4bed8b8c2d (patch) | |
| tree | 36cf415b78775ee63acdfc34d636d2b7d7936a78 /arch/mips/mach-ath79 | |
| parent | d15a244b059e361475302bccd471e65a48ee2b1f (diff) | |
| parent | d7d000311285e4b8d11e089ca13ea456a01be3b8 (diff) | |
| download | u-boot-imx-08ca213acadef61748dc62d48b0f5c4bed8b8c2d.zip u-boot-imx-08ca213acadef61748dc62d48b0f5c4bed8b8c2d.tar.gz u-boot-imx-08ca213acadef61748dc62d48b0f5c4bed8b8c2d.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/mips/mach-ath79')
21 files changed, 3870 insertions, 0 deletions
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig new file mode 100644 index 0000000..7d483aa --- /dev/null +++ b/arch/mips/mach-ath79/Kconfig @@ -0,0 +1,55 @@ +menu "QCA/Atheros 7xxx/9xxx platforms" + depends on ARCH_ATH79 + +config SYS_SOC + default "ath79" + +config SOC_AR933X + bool + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select MIPS_TUNE_24KC + help + This supports QCA/Atheros ar933x family SOCs. + +config SOC_AR934X + bool + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select MIPS_TUNE_74KC + help + This supports QCA/Atheros ar934x family SOCs. + +config SOC_QCA953X + bool + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select MIPS_TUNE_24KC + help + This supports QCA/Atheros qca953x family SOCs. + +choice + prompt "Board select" + +config TARGET_AP121 + bool "AP121 Reference Board" + select SOC_AR933X + +config TARGET_AP143 + bool "AP143 Reference Board" + select SOC_QCA953X + +config BOARD_TPLINK_WDR4300 + bool "TP-Link WDR4300 Board" + select SOC_AR934X + +endchoice + +source "board/qca/ap121/Kconfig" +source "board/qca/ap143/Kconfig" +source "board/tplink/wdr4300/Kconfig" + +endmenu diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile new file mode 100644 index 0000000..d7e2666 --- /dev/null +++ b/arch/mips/mach-ath79/Makefile @@ -0,0 +1,11 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += cpu.o +obj-y += dram.o + +obj-$(CONFIG_SOC_AR933X) += ar933x/ +obj-$(CONFIG_SOC_AR934X) += ar934x/ +obj-$(CONFIG_SOC_QCA953X) += qca953x/ diff --git a/arch/mips/mach-ath79/ar933x/Makefile b/arch/mips/mach-ath79/ar933x/Makefile new file mode 100644 index 0000000..fd74f0c --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/Makefile @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk.o +obj-y += ddr.o +obj-y += lowlevel_init.o diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c new file mode 100644 index 0000000..9fcd496 --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/clk.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +static u32 ar933x_get_xtal(void) +{ + u32 val; + + val = get_bootstrap(); + if (val & AR933X_BOOTSTRAP_REF_CLK_40) + return 40000000; + else + return 25000000; +} + +int get_serial_clock(void) +{ + return ar933x_get_xtal(); +} + +int get_clocks(void) +{ + void __iomem *regs; + u32 val, xtal, pll, div; + + regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, + MAP_NOCACHE); + xtal = ar933x_get_xtal(); + val = readl(regs + AR933X_PLL_CPU_CONFIG_REG); + + /* VCOOUT = XTAL * DIV_INT */ + div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) + & AR933X_PLL_CPU_CONFIG_REFDIV_MASK; + pll = xtal / div; + + /* PLLOUT = VCOOUT * (1/2^OUTDIV) */ + div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) + & AR933X_PLL_CPU_CONFIG_NINT_MASK; + pll *= div; + div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) + & AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; + if (!div) + div = 1; + pll >>= div; + + val = readl(regs + AR933X_PLL_CLK_CTRL_REG); + + /* CPU_CLK = PLLOUT / CPU_POST_DIV */ + div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) + & AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1; + gd->cpu_clk = pll / div; + + /* DDR_CLK = PLLOUT / DDR_POST_DIV */ + div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) + & AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1; + gd->mem_clk = pll / div; + + /* AHB_CLK = PLLOUT / AHB_POST_DIV */ + div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) + & AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1; + gd->bus_clk = pll / div; + + return 0; +} + +ulong get_bus_freq(ulong dummy) +{ + if (!gd->bus_clk) + get_clocks(); + return gd->bus_clk; +} + +ulong get_ddr_freq(ulong dummy) +{ + if (!gd->mem_clk) + get_clocks(); + return gd->mem_clk; +} diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c new file mode 100644 index 0000000..91452bc --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/ddr.c @@ -0,0 +1,333 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * Based on Atheros LSDK/QSDK + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DDR_CTRL_UPD_EMR3S BIT(5) +#define DDR_CTRL_UPD_EMR2S BIT(4) +#define DDR_CTRL_PRECHARGE BIT(3) +#define DDR_CTRL_AUTO_REFRESH BIT(2) +#define DDR_CTRL_UPD_EMRS BIT(1) +#define DDR_CTRL_UPD_MRS BIT(0) + +#define DDR_REFRESH_EN BIT(14) +#define DDR_REFRESH_M 0x3ff +#define DDR_REFRESH(x) ((x) & 0x3ff) +#define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390)) +#define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624)) + +#define DDR_TRAS_S 0 +#define DDR_TRAS_M 0x1f +#define DDR_TRAS(x) ((x) << DDR_TRAS_S) +#define DDR_TRCD_M 0xf +#define DDR_TRCD_S 5 +#define DDR_TRCD(x) ((x) << DDR_TRCD_S) +#define DDR_TRP_M 0xf +#define DDR_TRP_S 9 +#define DDR_TRP(x) ((x) << DDR_TRP_S) +#define DDR_TRRD_M 0xf +#define DDR_TRRD_S 13 +#define DDR_TRRD(x) ((x) << DDR_TRRD_S) +#define DDR_TRFC_M 0x7f +#define DDR_TRFC_S 17 +#define DDR_TRFC(x) ((x) << DDR_TRFC_S) +#define DDR_TMRD_M 0xf +#define DDR_TMRD_S 23 +#define DDR_TMRD(x) ((x) << DDR_TMRD_S) +#define DDR_CAS_L_M 0x17 +#define DDR_CAS_L_S 27 +#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S) +#define DDR_OPEN BIT(30) +#define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \ + DDR_TRP(6) | DDR_TRRD(4) | \ + DDR_TRFC(30) | DDR_TMRD(15) | \ + DDR_CAS_L(7) | DDR_OPEN) + +#define DDR_BURST_LEN_S 0 +#define DDR_BURST_LEN_M 0xf +#define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S) +#define DDR_BURST_TYPE BIT(4) +#define DDR_CNTL_OE_EN BIT(5) +#define DDR_PHASE_SEL BIT(6) +#define DDR_CKE BIT(7) +#define DDR_TWR_S 8 +#define DDR_TWR_M 0xf +#define DDR_TWR(x) ((x) << DDR_TWR_S) +#define DDR_TRTW_S 12 +#define DDR_TRTW_M 0x1f +#define DDR_TRTW(x) ((x) << DDR_TRTW_S) +#define DDR_TRTP_S 17 +#define DDR_TRTP_M 0xf +#define DDR_TRTP(x) ((x) << DDR_TRTP_S) +#define DDR_TWTR_S 21 +#define DDR_TWTR_M 0x1f +#define DDR_TWTR(x) ((x) << DDR_TWTR_S) +#define DDR_G_OPEN_L_S 26 +#define DDR_G_OPEN_L_M 0xf +#define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S) +#define DDR_HALF_WIDTH_LOW BIT(31) +#define DDR_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \ + DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \ + DDR_TRTP(8) | DDR_TWTR(14) | \ + DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW) + +#define DDR2_CONF_TWL_S 10 +#define DDR2_CONF_TWL_M 0xf +#define DDR2_CONF_TWL(x) (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S) +#define DDR2_CONF_ODT BIT(9) +#define DDR2_CONF_TFAW_S 2 +#define DDR2_CONF_TFAW_M 0x3f +#define DDR2_CONF_TFAW(x) (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S) +#define DDR2_CONF_EN BIT(0) +#define DDR2_CONF_VAL (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \ + DDR2_CONF_TFAW(22) | DDR2_CONF_EN) + +#define DDR1_EXT_MODE_VAL 0x02 +#define DDR2_EXT_MODE_VAL 0x402 +#define DDR2_EXT_MODE_OCD_VAL 0x382 +#define DDR1_MODE_DLL_VAL 0x133 +#define DDR2_MODE_DLL_VAL 0x100 +#define DDR1_MODE_VAL 0x33 +#define DDR2_MODE_VAL 0xa33 +#define DDR_TAP_VAL0 0x08 +#define DDR_TAP_VAL1 0x09 + +void ddr_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, + MAP_NOCACHE); + + writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); + writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); + + val = get_bootstrap(); + if (val & AR933X_BOOTSTRAP_DDR2) { + /* AHB maximum timeout */ + writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX); + + /* Enable DDR2 */ + writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG); + + /* Precharge All */ + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); + + /* Disable High Temperature Self-Refresh, Full Array */ + writel(0x00, regs + AR933X_DDR_REG_EMR2); + + /* Extended Mode Register 2 Set (EMR2S) */ + writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); + + writel(0x00, regs + AR933X_DDR_REG_EMR3); + + /* Extended Mode Register 3 Set (EMR3S) */ + writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); + + /* Enable DLL, Full strength, ODT Disabled */ + writel(0x00, regs + AR71XX_DDR_REG_EMR); + + /* Extended Mode Register Set (EMRS) */ + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); + + /* Reset DLL */ + writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); + + /* Mode Register Set (MRS) */ + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); + + /* Precharge All */ + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); + + /* Auto Refresh */ + writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); + writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); + + /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */ + writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE); + /* Mode Register Set (MRS) */ + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); + + /* Enable OCD defaults, Enable DLL, Reduced Drive Strength */ + writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR); + + /* Extended Mode Register Set (EMRS) */ + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); + + /* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */ + writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); + /* Extended Mode Register Set (EMRS) */ + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); + + /* Refresh time control */ + if (val & AR933X_BOOTSTRAP_REF_CLK_40) + writel(DDR_REFRESH_VAL_40M, regs + + AR71XX_DDR_REG_REFRESH); + else + writel(DDR_REFRESH_VAL_25M, regs + + AR71XX_DDR_REG_REFRESH); + + /* DQS 0 Tap Control */ + writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0); + + /* DQS 1 Tap Control */ + writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); + + /* For 16-bit DDR */ + writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE); + } else { + /* AHB maximum timeout */ + writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX); + + /* Precharge All */ + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); + + /* Reset DLL, Burst Length 8, CAS Latency 3 */ + writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); + + /* Forces an MRS update cycle in DDR */ + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); + + /* Enable DLL, Full strength */ + writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); + + /* Extended Mode Register Set (EMRS) */ + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); + + /* Precharge All */ + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); + + /* Normal DLL, Burst Length 8, CAS Latency 3 */ + writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE); + + /* Mode Register Set (MRS) */ + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); + + /* Refresh time control */ + if (val & AR933X_BOOTSTRAP_REF_CLK_40) + writel(DDR_REFRESH_VAL_40M, regs + + AR71XX_DDR_REG_REFRESH); + else + writel(DDR_REFRESH_VAL_25M, regs + + AR71XX_DDR_REG_REFRESH); + + /* DQS 0 Tap Control */ + writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0); + + /* DQS 1 Tap Control */ + writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); + + /* For 16-bit DDR */ + writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE); + } +} + +void ddr_tap_tuning(void) +{ + void __iomem *regs; + u32 *addr_k0, *addr_k1, *addr; + u32 val, tap, upper, lower; + int i, j, dir, err, done; + + regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, + MAP_NOCACHE); + + /* Init memory pattern */ + addr = (void *)CKSEG0ADDR(0x2000); + for (i = 0; i < 256; i++) { + val = 0; + for (j = 0; j < 8; j++) { + if (i & (1 << j)) { + if (j % 2) + val |= 0xffff0000; + else + val |= 0x0000ffff; + } + + if (j % 2) { + *addr++ = val; + val = 0; + } + } + } + + err = 0; + done = 0; + dir = 1; + tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); + val = tap; + while (!done) { + err = 0; + + /* Update new DDR tap value */ + writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0); + writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); + + /* Compare DDR with cache */ + for (i = 0; i < 2; i++) { + addr_k1 = (void *)CKSEG1ADDR(0x2000); + addr_k0 = (void *)CKSEG0ADDR(0x2000); + addr = (void *)CKSEG0ADDR(0x3000); + + while (addr_k0 < addr) { + if (*addr_k1++ != *addr_k0++) { + err = 1; + break; + } + } + + if (err) + break; + } + + if (err) { + /* Save upper/lower threshold if error */ + if (dir) { + dir = 0; + val--; + upper = val; + val = tap; + } else { + val++; + lower = val; + done = 1; + } + } else { + /* Try the next value until limitation */ + if (dir) { + if (val < 0x20) { + val++; + } else { + dir = 0; + upper = val; + val = tap; + } + } else { + if (!val) { + lower = val; + done = 1; + } else { + val--; + } + } + } + } + + /* compute an intermediate value and write back */ + val = (upper + lower) / 2; + writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0); + val++; + writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); +} diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..1b847f5 --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * Based on Atheros LSDK/QSDK and u-boot_mod project + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <mach/ar71xx_regs.h> + +#define SET_BIT(val, bit) ((val) | (1 << (bit))) +#define SET_PLL_PD(val) SET_BIT(val, 30) +#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) +#define PLL_BYPASS(val) SET_BIT(val, 2) + +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ + (((0x3F & divint) << 10) | \ + ((0x1F & refdiv) << 16) | \ + ((0x1 & range) << 21) | \ + ((0x7 & outdiv) << 23) ) + +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ + (((0x3 & (cpudiv - 1)) << 5) | \ + ((0x3 & (ddrdiv - 1)) << 10) | \ + ((0x3 & (ahbdiv - 1)) << 15) ) + +/* + * PLL_CPU_CONFIG_VAL + * + * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU PLL Configuration (CPU_PLL_CONFIG) + * + * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL) + * => 32 (0x20) VCOOUT = XTAL * DIV_INT + * bits 16..20 (5bit) REFDIV (Reference clock divider) + * => 1 (0x1) [Must start at values 1] + * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL) + * => 0 (0x0) [Doesn't impact clock values] + * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output) + * => 1 (0x1) [0 is illegal!] + * PLLOUT = VCOOUT * (1/2^OUTDIV) + */ +/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1) + +/* + * PLL_CLK_CONTROL_VAL + * + * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU Clock Control Register CLOCK_CONTROL + * + * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test. + * Software must enable the CPU PLL for normal and + * then set this bit to 0) + * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) + * CPU_CLK = PLLOUT / CPU_POST_DIV + * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) + * DDR_CLK = PLLOUT / DDR_POST_DIV + * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) + * AHB_CLK = PLLOUT / AHB_POST_DIV + * + */ +#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2) + + .text + .set noreorder + +LEAF(lowlevel_init) + /* These three WLAN_RESET will avoid original issue */ + li t3, 0x03 +1: + li t0, CKSEG1ADDR(AR71XX_RESET_BASE) + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) + ori t1, t1, 0x0800 + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) + nop + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) + li t2, 0xfffff7ff + and t1, t1, t2 + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) + nop + addi t3, t3, -1 + bnez t3, 1b + nop + + li t2, 0x20 +2: + beqz t2, 1b + nop + addi t2, t2, -1 + lw t5, AR933X_RESET_REG_BOOTSTRAP(t0) + andi t1, t5, 0x10 + bnez t1, 2b + nop + + li t1, 0x02110E + sw t1, AR933X_RESET_REG_BOOTSTRAP(t0) + nop + + /* RTC Force Wake */ + li t0, CKSEG1ADDR(AR933X_RTC_BASE) + li t1, 0x03 + sw t1, AR933X_RTC_REG_FORCE_WAKE(t0) + nop + nop + + /* RTC Reset */ + li t1, 0x00 + sw t1, AR933X_RTC_REG_RESET(t0) + nop + nop + + li t1, 0x01 + sw t1, AR933X_RTC_REG_RESET(t0) + nop + nop + + /* Wait for RTC in on state */ +1: + lw t1, AR933X_RTC_REG_STATUS(t0) + andi t1, t1, 0x02 + beqz t1, 1b + nop + + /* Program ki/kd */ + li t0, CKSEG1ADDR(AR933X_SRIF_BASE) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x19e82f01 + b 2f + nop +1: + li t1, 0x18e82f01 +2: + sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0) + + /* Program phase shift */ + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0xc07fffff + and t1, t1, t2 + li t2, 0x800000 + or t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + /* in some cases, the SoC doesn't start with higher clock on AHB */ + li t0, CKSEG1ADDR(AR71XX_PLL_BASE) + li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL)) + sw t1, AR933X_PLL_CLK_CTRL_REG(t0) + nop + + /* Set SETTLE_TIME in CPU PLL */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x0352 + b 2f + nop +1: + li t1, 0x0550 +2: + sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0) + nop + + /* Set nint, frac, refdiv, outdiv, range according to xtal */ +0: + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M) + b 2f + nop +1: + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M) +2: + sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + nop +1: + lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Put frac bit19:10 configuration */ + li t1, 0x1003E8 + sw t1, AR933X_PLL_DITHER_FRAC_REG(t0) + nop + + /* Clear PLL power down bit in CPU PLL configuration */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, PLL_CPU_CONFIG_VAL_25M + b 2f + nop +1: + li t1, PLL_CPU_CONFIG_VAL_40M +2: + sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + nop + + /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */ +1: + lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Confirm DDR PLL lock */ + li t3, 100 + li t4, 0 + +2: + addi t4, t4, 1 + bgt t4, t3, 0b + nop + + li t3, 5 +3: + /* Clear do_meas */ + li t0, CKSEG1ADDR(AR933X_SRIF_BASE) + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0xBFFFFFFF + and t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + li t2, 10 +1: + subu t2, t2, 1 + bnez t2, 1b + nop + + /* Set do_meas */ + li t2, 0x40000000 + or t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + /* Check meas_done */ +1: + lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0) + andi t1, t1, 0x8 + beqz t1, 1b + nop + + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0x007FFFF8 + and t1, t1, t2 + srl t1, t1, 3 + li t2, 0x4000 + bgt t1, t2, 2b + nop + addi t3, t3, -1 + bnez t3, 3b + nop + + /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ + li t0, CKSEG1ADDR(AR71XX_PLL_BASE) + li t1, PLL_CLK_CONTROL_VAL + sw t1, AR933X_PLL_CLK_CTRL_REG(t0) + nop + + nop + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-ath79/ar934x/Makefile b/arch/mips/mach-ath79/ar934x/Makefile new file mode 100644 index 0000000..348c65b --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/Makefile @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += clk.o +obj-y += ddr.o diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c new file mode 100644 index 0000000..9c65184 --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/clk.c @@ -0,0 +1,334 @@ +/* + * Copyright (C) 2016 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> +#include <wait_bit.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The math for calculating PLL: + * NFRAC * 2^8 + * NINT + ------------- + * XTAL [MHz] 2^(18 - 1) + * PLL [MHz] = ------------ * ---------------------- + * REFDIV 2^OUTDIV + * + * Unfortunatelly, there is no way to reliably compute the variables. + * The vendor U-Boot port contains macros for various combinations of + * CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern + * in those numbers. + */ +struct ar934x_pll_config { + u8 range; + u8 refdiv; + u8 outdiv; + /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */ + u8 nint[2]; +}; + +struct ar934x_clock_config { + u16 cpu_freq; + u16 ddr_freq; + u16 ahb_freq; + + struct ar934x_pll_config cpu_pll; + struct ar934x_pll_config ddr_pll; +}; + +static const struct ar934x_clock_config ar934x_clock_config[] = { + { 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } }, + { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } }, + { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } }, + { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } }, + { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } }, + { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } }, + { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } }, + { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } }, + { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } }, + { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } }, + { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } }, + { 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } }, + { 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } }, + { 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } }, + { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } }, + { 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } }, + { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } }, + { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } }, + { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } }, + { 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } }, + { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } }, + { 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } }, + { 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } }, + { 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } }, + { 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } }, + { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } }, + { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } }, + { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } }, +}; + +static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) +{ + u32 reg; + do { + writel(0x10810f00, pll_reg_base + 0x4); + writel(srif_val, pll_reg_base + 0x0); + writel(0xd0810f00, pll_reg_base + 0x4); + writel(0x03000000, pll_reg_base + 0x8); + writel(0xd0800f00, pll_reg_base + 0x4); + + clrbits_be32(pll_reg_base + 0x8, BIT(30)); + udelay(5); + setbits_be32(pll_reg_base + 0x8, BIT(30)); + udelay(5); + + wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0); + + clrbits_be32(pll_reg_base + 0x8, BIT(30)); + udelay(5); + + /* Check if CPU SRIF PLL locked. */ + reg = readl(pll_reg_base + 0x8); + reg = (reg & 0x7ffff8) >> 3; + } while (reg >= 0x40000); +} + +void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) +{ + void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE, + AR934X_SRIF_SIZE, MAP_NOCACHE); + void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, + AR71XX_PLL_SIZE, MAP_NOCACHE); + const struct ar934x_pll_config *pll_cfg; + int i, pll_nint, pll_refdiv, xtal_40 = 0; + u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif; + + /* Configure SRIF PLL with initial values. */ + writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG); + writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG); + writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG); + writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG); + writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */ + + /* Test for 40MHz XTAL */ + reg = get_bootstrap(); + if (reg & AR934X_BOOTSTRAP_REF_CLK_40) { + xtal_40 = 1; + cpu_srif = 0x41c00000; + ddr_srif = 0x41680000; + } else { + xtal_40 = 0; + cpu_srif = 0x29c00000; + ddr_srif = 0x29680000; + } + + /* Locate CPU/DDR PLL configuration */ + for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) { + if (cpu_mhz != ar934x_clock_config[i].cpu_freq) + continue; + if (ddr_mhz != ar934x_clock_config[i].ddr_freq) + continue; + if (ahb_mhz != ar934x_clock_config[i].ahb_freq) + continue; + + /* Entry found */ + pll_cfg = &ar934x_clock_config[i].cpu_pll; + pll_nint = pll_cfg->nint[xtal_40]; + pll_refdiv = pll_cfg->refdiv; + cpu_pll = + (pll_nint << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) | + (pll_refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) | + (pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) | + (pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT); + + pll_cfg = &ar934x_clock_config[i].ddr_pll; + pll_nint = pll_cfg->nint[xtal_40]; + pll_refdiv = pll_cfg->refdiv; + ddr_pll = + (pll_nint << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) | + (pll_refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) | + (pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) | + (pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT); + break; + } + + /* PLL configuration not found, hang. */ + if (i == ARRAY_SIZE(ar934x_clock_config)) + hang(); + + /* Set PLL Bypass */ + setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS); + setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); + setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS); + + /* Configure CPU PLL */ + writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD, + pll_regs + AR934X_PLL_CPU_CONFIG_REG); + /* Configure DDR PLL */ + writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD, + pll_regs + AR934X_PLL_DDR_CONFIG_REG); + /* Configure PLL routing */ + writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS | + AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | + AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS | + (0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) | + (0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) | + (1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) | + AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | + AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL | + AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL, + pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); + + /* Configure SRIF PLLs, which is completely undocumented :-) */ + ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif); + ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif); + + /* Unset PLL Bypass */ + clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS); + clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); + clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS); + + /* Enable PLL dithering */ + writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) | + (0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT), + pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG); + writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT, + pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG); +} + +static u32 ar934x_get_xtal(void) +{ + u32 val; + + val = get_bootstrap(); + if (val & AR934X_BOOTSTRAP_REF_CLK_40) + return 40000000; + else + return 25000000; +} + +int get_serial_clock(void) +{ + return ar934x_get_xtal(); +} + +static u32 ar934x_cpupll_to_hz(const u32 regval) +{ + const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; + const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_REFDIV_MASK; + const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & + AR934X_PLL_CPU_CONFIG_NINT_MASK; + const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_CPU_CONFIG_NFRAC_MASK; + const u32 xtal = ar934x_get_xtal(); + + return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); +} + +static u32 ar934x_ddrpll_to_hz(const u32 regval) +{ + const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; + const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_REFDIV_MASK; + const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & + AR934X_PLL_DDR_CONFIG_NINT_MASK; + const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_DDR_CONFIG_NFRAC_MASK; + const u32 xtal = ar934x_get_xtal(); + + return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); +} + +static void ar934x_update_clock(void) +{ + void __iomem *regs; + u32 ctrl, cpu, cpupll, ddr, ddrpll; + u32 cpudiv, ddrdiv, busdiv; + u32 cpuclk, ddrclk, busclk; + + regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, + MAP_NOCACHE); + + cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG); + ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG); + ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); + + cpupll = ar934x_cpupll_to_hz(cpu); + ddrpll = ar934x_ddrpll_to_hz(ddr); + + if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS) + cpuclk = ar934x_get_xtal(); + else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) + cpuclk = cpupll; + else + cpuclk = ddrpll; + + if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) + ddrclk = ar934x_get_xtal(); + else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) + ddrclk = ddrpll; + else + ddrclk = cpupll; + + if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS) + busclk = ar934x_get_xtal(); + else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) + busclk = ddrpll; + else + busclk = cpupll; + + cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & + AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; + ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & + AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; + busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & + AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; + + gd->cpu_clk = cpuclk / (cpudiv + 1); + gd->mem_clk = ddrclk / (ddrdiv + 1); + gd->bus_clk = busclk / (busdiv + 1); +} + +ulong get_bus_freq(ulong dummy) +{ + ar934x_update_clock(); + return gd->bus_clk; +} + +ulong get_ddr_freq(ulong dummy) +{ + ar934x_update_clock(); + return gd->mem_clk; +} + +int do_ar934x_showclk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ar934x_update_clock(); + printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000); + printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000); + printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000); + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk, + "display clocks", + "" +); diff --git a/arch/mips/mach-ath79/ar934x/cpu.c b/arch/mips/mach-ath79/ar934x/cpu.c new file mode 100644 index 0000000..8fcdf65 --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/cpu.c @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +/* The lowlevel_init() is not needed on AR934x */ +void lowlevel_init(void) {} diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c new file mode 100644 index 0000000..4621d58 --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/ddr.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2016 Marek Vasut <marex@denx.de> + * + * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + AR934X_SDRAM = 0, + AR934X_DDR1, + AR934X_DDR2, +}; + +struct ar934x_mem_config { + u32 config1; + u32 config2; + u32 mode; + u32 extmode; + u32 tap; +}; + +static const struct ar934x_mem_config ar934x_mem_config[] = { + [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f }, + [AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 }, + [AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 }, +}; + +void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) +{ + void __iomem *ddr_regs; + const struct ar934x_mem_config *memcfg; + int memtype; + u32 reg, cycle, ctl; + + ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, + MAP_NOCACHE); + + reg = get_bootstrap(); + if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */ + if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */ + memtype = AR934X_DDR1; + cycle = 0xffff; + } else { /* DDR 2 */ + memtype = AR934X_DDR2; + if (gd->arch.rev) { + ctl = BIT(6); /* Undocumented bit :-( */ + if (reg & BIT(3)) + cycle = 0xff; + else + cycle = 0xffff; + } else { + /* Force DDR2/x16 configuratio on old chips. */ + ctl = 0; + cycle = 0xffff; /* DDR2 16bit */ + } + + writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG); + udelay(100); + + writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF); + udelay(10); + } + } else { /* SDRAM */ + memtype = AR934X_SDRAM; + cycle = 0xffffffff; + + writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF); + udelay(100); + + /* Undocumented register */ + writel(0x13b, ddr_regs + 0x118); + udelay(100); + } + + memcfg = &ar934x_mem_config[memtype]; + + writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG); + udelay(100); + + writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2); + udelay(100); + + writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE); + mdelay(1); + + writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + if (memtype == AR934X_DDR2) { + writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR); + udelay(100); + + writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + } + + if (memtype != AR934X_SDRAM) + writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR); + + udelay(100); + + writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE); + udelay(100); + + writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH); + udelay(100); + + writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); + writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); + + if (memtype != AR934X_SDRAM) { + if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) { + writel(memcfg->tap, + ddr_regs + AR934X_DDR_REG_TAP_CTRL2); + writel(memcfg->tap, + ddr_regs + AR934X_DDR_REG_TAP_CTRL3); + } + } + + writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); + udelay(100); + + writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST); + udelay(100); + + writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2); + udelay(100); + + writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX); + udelay(100); +} + +void ddr_tap_tuning(void) +{ +} diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c new file mode 100644 index 0000000..5756a06 --- /dev/null +++ b/arch/mips/mach-ath79/cpu.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ath79.h> +#include <mach/ar71xx_regs.h> + +struct ath79_soc_desc { + const enum ath79_soc_type soc; + const char *chip; + const int major; + const int minor; +}; + +static const struct ath79_soc_desc desc[] = { + {ATH79_SOC_AR7130, "7130", + REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130}, + {ATH79_SOC_AR7141, "7141", + REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7141}, + {ATH79_SOC_AR7161, "7161", + REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7161}, + {ATH79_SOC_AR7240, "7240", REV_ID_MAJOR_AR7240, 0}, + {ATH79_SOC_AR7241, "7241", REV_ID_MAJOR_AR7241, 0}, + {ATH79_SOC_AR7242, "7242", REV_ID_MAJOR_AR7242, 0}, + {ATH79_SOC_AR9130, "9130", + REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9130}, + {ATH79_SOC_AR9132, "9132", + REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9132}, + {ATH79_SOC_AR9330, "9330", REV_ID_MAJOR_AR9330, 0}, + {ATH79_SOC_AR9331, "9331", REV_ID_MAJOR_AR9331, 0}, + {ATH79_SOC_AR9341, "9341", REV_ID_MAJOR_AR9341, 0}, + {ATH79_SOC_AR9342, "9342", REV_ID_MAJOR_AR9342, 0}, + {ATH79_SOC_AR9344, "9344", REV_ID_MAJOR_AR9344, 0}, + {ATH79_SOC_QCA9533, "9533", REV_ID_MAJOR_QCA9533, 0}, + {ATH79_SOC_QCA9533, "9533", + REV_ID_MAJOR_QCA9533_V2, 0}, + {ATH79_SOC_QCA9556, "9556", REV_ID_MAJOR_QCA9556, 0}, + {ATH79_SOC_QCA9558, "9558", REV_ID_MAJOR_QCA9558, 0}, + {ATH79_SOC_TP9343, "9343", REV_ID_MAJOR_TP9343, 0}, + {ATH79_SOC_QCA9561, "9561", REV_ID_MAJOR_QCA9561, 0}, +}; + +int arch_cpu_init(void) +{ + void __iomem *base; + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; + u32 id, major, minor = 0; + u32 rev = 0, ver = 1; + int i; + + base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, + MAP_NOCACHE); + + id = readl(base + AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; + switch (major) { + case REV_ID_MAJOR_AR71XX: + case REV_ID_MAJOR_AR913X: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9533_V2: + ver = 2; + /* drop through */ + + case REV_ID_MAJOR_AR9341: + case REV_ID_MAJOR_AR9342: + case REV_ID_MAJOR_AR9344: + case REV_ID_MAJOR_QCA9533: + case REV_ID_MAJOR_QCA9556: + case REV_ID_MAJOR_QCA9558: + case REV_ID_MAJOR_TP9343: + case REV_ID_MAJOR_QCA9561: + rev = id & AR71XX_REV_ID_REVISION2_MASK; + break; + default: + rev = id & AR71XX_REV_ID_REVISION_MASK; + break; + } + + for (i = 0; i < ARRAY_SIZE(desc); i++) { + if ((desc[i].major == major) && + (desc[i].minor == minor)) { + soc = desc[i].soc; + break; + } + } + + gd->arch.id = id; + gd->arch.soc = soc; + gd->arch.rev = rev; + gd->arch.ver = ver; + return 0; +} + +int print_cpuinfo(void) +{ + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; + const char *chip = "????"; + u32 id, rev, ver; + int i; + + for (i = 0; i < ARRAY_SIZE(desc); i++) { + if (desc[i].soc == gd->arch.soc) { + chip = desc[i].chip; + soc = desc[i].soc; + break; + } + } + + id = gd->arch.id; + rev = gd->arch.rev; + ver = gd->arch.ver; + + switch (soc) { + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip, + ver, rev); + break; + case ATH79_SOC_TP9343: + printf("Qualcomm Atheros TP%s rev %u\n", chip, rev); + break; + case ATH79_SOC_UNKNOWN: + printf("ATH79: unknown SoC, id:0x%08x", id); + break; + default: + printf("Atheros AR%s rev %u\n", chip, rev); + } + + return 0; +} diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c new file mode 100644 index 0000000..c29e98c --- /dev/null +++ b/arch/mips/mach-ath79/dram.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/sizes.h> +#include <asm/addrspace.h> +#include <mach/ddr.h> + +phys_size_t initdram(int board_type) +{ + ddr_tap_tuning(); + return get_ram_size((void *)KSEG1, SZ_256M); +} diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..a8e51cb --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -0,0 +1,1263 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif +#endif + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE \ + (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE \ + (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE \ + (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE \ + (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE \ + (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE \ + (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE \ + (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE \ + (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE \ + (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE \ + (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_RTC_BASE \ + (AR71XX_APB_BASE + 0x00107000) +#define AR933X_RTC_SIZE 0x1000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 +#define AR933X_SRIF_BASE \ + (AR71XX_APB_BASE + 0x00116000) +#define AR933X_SRIF_SIZE 0x1000 + +#define AR934X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 +#define AR934X_NFC_BASE 0x1b000200 +#define AR934X_NFC_SIZE 0xb8 +#define AR934X_SRIF_BASE \ + (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 + +#define QCA953X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define QCA953X_GMAC_SIZE 0x14 +#define QCA953X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define QCA953X_WMAC_SIZE 0x20000 +#define QCA953X_RTC_BASE \ + (AR71XX_APB_BASE + 0x00107000) +#define QCA953X_RTC_SIZE 0x1000 +#define QCA953X_EHCI_BASE 0x1b000000 +#define QCA953X_EHCI_SIZE 0x200 +#define QCA953X_SRIF_BASE \ + (AR71XX_APB_BASE + 0x00116000) +#define QCA953X_SRIF_SIZE 0x1000 + +#define QCA953X_PCI_CFG_BASE0 0x14000000 +#define QCA953X_PCI_CTRL_BASE0 \ + (AR71XX_APB_BASE + 0x000f0000) +#define QCA953X_PCI_CRP_BASE0 \ + (AR71XX_APB_BASE + 0x000c0000) +#define QCA953X_PCI_MEM_BASE0 0x10000000 +#define QCA953X_PCI_MEM_SIZE 0x02000000 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 \ + (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 \ + (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 \ + (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 \ + (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 +#define QCA955X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 + +#define QCA956X_PCI_MEM_BASE1 0x12000000 +#define QCA956X_PCI_MEM_SIZE 0x02000000 +#define QCA956X_PCI_CFG_BASE1 0x16000000 +#define QCA956X_PCI_CFG_SIZE 0x1000 +#define QCA956X_PCI_CRP_BASE1 \ + (AR71XX_APB_BASE + 0x00250000) +#define QCA956X_PCI_CRP_SIZE 0x1000 +#define QCA956X_PCI_CTRL_BASE1 \ + (AR71XX_APB_BASE + 0x00280000) +#define QCA956X_PCI_CTRL_SIZE 0x100 + +#define QCA956X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define QCA956X_WMAC_SIZE 0x20000 +#define QCA956X_EHCI0_BASE 0x1b000000 +#define QCA956X_EHCI1_BASE 0x1b400000 +#define QCA956X_EHCI_SIZE 0x200 +#define QCA956X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define QCA956X_GMAC_SIZE 0x64 + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_CONFIG 0x00 +#define AR71XX_DDR_REG_CONFIG2 0x04 +#define AR71XX_DDR_REG_MODE 0x08 +#define AR71XX_DDR_REG_EMR 0x0c +#define AR71XX_DDR_REG_CONTROL 0x10 +#define AR71XX_DDR_REG_REFRESH 0x14 +#define AR71XX_DDR_REG_RD_CYCLE 0x18 +#define AR71XX_DDR_REG_TAP_CTRL0 0x1c +#define AR71XX_DDR_REG_TAP_CTRL1 0x20 + +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_DDR2_CONFIG 0x8c +#define AR933X_DDR_REG_EMR2 0x90 +#define AR933X_DDR_REG_EMR3 0x94 +#define AR933X_DDR_REG_BURST 0x98 +#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c +#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c +#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c + +#define AR934X_DDR_REG_TAP_CTRL2 0x24 +#define AR934X_DDR_REG_TAP_CTRL3 0x28 +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac +#define AR934X_DDR_REG_FLUSH_SRC1 0xb0 +#define AR934X_DDR_REG_FLUSH_SRC2 0xb4 +#define AR934X_DDR_REG_DDR2_CONFIG 0xb8 +#define AR934X_DDR_REG_EMR2 0xbc +#define AR934X_DDR_REG_EMR3 0xc0 +#define AR934X_DDR_REG_BURST 0xc4 +#define AR934X_DDR_REG_BURST2 0xc8 +#define AR934X_DDR_REG_TIMEOUT_MAX 0xcc +#define AR934X_DDR_REG_CTL_CONF 0x108 + +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac +#define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 +#define QCA953X_DDR_REG_BURST 0xc4 +#define QCA953X_DDR_REG_BURST2 0xc8 +#define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc +#define QCA953X_DDR_REG_CTL_CONF 0x108 +#define QCA953X_DDR_REG_CONFIG3 0x15c + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLK_CTRL_REG 0x08 +#define AR933X_PLL_DITHER_FRAC_REG 0x10 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 +#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 +#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define AR934X_PLL_DDR_DIT_FRAC_REG 0x44 +#define AR934X_PLL_CPU_DIT_FRAC_REG 0x48 + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_RANGE_SHIFT 17 +#define AR934X_PLL_CPU_CONFIG_RANGE_MASK 0x3 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 +#define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30) +#define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31) + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_RANGE_SHIFT 21 +#define AR934X_PLL_DDR_CONFIG_RANGE_MASK 0x3 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 +#define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30) +#define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31) + +#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) + +#define AR934X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 +#define AR934X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff +#define AR934X_PLL_DDR_DIT_FRAC_MIN_SHIFT 10 +#define AR934X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff +#define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 +#define AR934X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f +#define AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 +#define AR934X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f +#define AR934X_PLL_DDR_DIT_DITHER_EN BIT(31) + +#define AR934X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 +#define AR934X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f +#define AR934X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 +#define AR934X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f +#define AR934X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 +#define AR934X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f +#define AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 +#define AR934X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f +#define AR934X_PLL_CPU_DIT_DITHER_EN BIT(31) + +#define QCA953X_PLL_CPU_CONFIG_REG 0x00 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04 +#define QCA953X_PLL_CLK_CTRL_REG 0x08 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 +#define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 + +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_CONFIG_PWD BIT(30) + +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 +#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 +#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 +#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 +#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f + +#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 +#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff +#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 +#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff +#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 +#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f +#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 +#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f + +#define QCA953X_PLL_DIT_FRAC_EN BIT(31) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA956X_PLL_CPU_CONFIG_REG 0x00 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c +#define QCA956X_PLL_CLK_CTRL_REG 0x10 + +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA953X_RESET_REG_RESET_MODULE 0x1c +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_RESET_MODULE 0x1c +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define QCA956X_RESET_REG_RESET_MODULE 0x1c +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_ETH_SWITCH BIT(8) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define QCA953X_RESET_USB_EXT_PWR BIT(29) +#define QCA953X_RESET_EXTERNAL BIT(28) +#define QCA953X_RESET_RTC BIT(27) +#define QCA953X_RESET_FULL_CHIP BIT(24) +#define QCA953X_RESET_GE1_MDIO BIT(23) +#define QCA953X_RESET_GE0_MDIO BIT(22) +#define QCA953X_RESET_CPU_NMI BIT(21) +#define QCA953X_RESET_CPU_COLD BIT(20) +#define QCA953X_RESET_DDR BIT(16) +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA953X_RESET_GE1_MAC BIT(13) +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA953X_RESET_GE0_MAC BIT(9) +#define QCA953X_RESET_ETH_SWITCH BIT(8) +#define QCA953X_RESET_PCIE_PHY BIT(7) +#define QCA953X_RESET_PCIE BIT(6) +#define QCA953X_RESET_USB_HOST BIT(5) +#define QCA953X_RESET_USB_PHY BIT(4) +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) +#define QCA955X_RESET_EXTERNAL BIT(28) +#define QCA955X_RESET_RTC BIT(27) +#define QCA955X_RESET_PCIE_EP_INT BIT(26) +#define QCA955X_RESET_CHKSUM_ACC BIT(25) +#define QCA955X_RESET_FULL_CHIP BIT(24) +#define QCA955X_RESET_GE1_MDIO BIT(23) +#define QCA955X_RESET_GE0_MDIO BIT(22) +#define QCA955X_RESET_CPU_NMI BIT(21) +#define QCA955X_RESET_CPU_COLD BIT(20) +#define QCA955X_RESET_HOST_RESET_INT BIT(19) +#define QCA955X_RESET_PCIE_EP BIT(18) +#define QCA955X_RESET_UART1 BIT(17) +#define QCA955X_RESET_DDR BIT(16) +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA955X_RESET_NANDF BIT(14) +#define QCA955X_RESET_GE1_MAC BIT(13) +#define QCA955X_RESET_SGMII_ANALOG BIT(12) +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA955X_RESET_HOST_DMA_INT BIT(10) +#define QCA955X_RESET_GE0_MAC BIT(9) +#define QCA955X_RESET_SGMII BIT(8) +#define QCA955X_RESET_PCIE_PHY BIT(7) +#define QCA955X_RESET_PCIE BIT(6) +#define QCA955X_RESET_USB_HOST BIT(5) +#define QCA955X_RESET_USB_PHY BIT(4) +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_DDR2 BIT(13) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define QCA953X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) + +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define QCA956X_EXT_INT_WMAC_MISC BIT(0) +#define QCA956X_EXT_INT_WMAC_TX BIT(1) +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA956X_EXT_INT_USB1 BIT(24) +#define QCA956X_EXT_INT_USB2 BIT(28) + +#define QCA956X_EXT_INT_WMAC_ALL \ + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) + +#define QCA956X_EXT_INT_PCIE_RC1_ALL \ + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ + QCA956X_EXT_INT_PCIE_RC1_INT3) + +#define QCA956X_EXT_INT_PCIE_RC2_ALL \ + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ + QCA956X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9533 0x0140 +#define REV_ID_MAJOR_QCA9533_V2 0x0160 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 +#define REV_ID_MAJOR_TP9343 0x0150 +#define REV_ID_MAJOR_QCA9561 0x1150 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 + +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 +#define AR71XX_REV_ID_REVISION2_MASK 0xf + +/* + * RTC block + */ +#define AR933X_RTC_REG_RESET 0x40 +#define AR933X_RTC_REG_STATUS 0x44 +#define AR933X_RTC_REG_DERIVED 0x48 +#define AR933X_RTC_REG_FORCE_WAKE 0x4c +#define AR933X_RTC_REG_INT_CAUSE 0x50 +#define AR933X_RTC_REG_CAUSE_CLR 0x50 +#define AR933X_RTC_REG_INT_ENABLE 0x54 +#define AR933X_RTC_REG_INT_MASKE 0x58 + +#define QCA953X_RTC_REG_SYNC_RESET 0x40 +#define QCA953X_RTC_REG_SYNC_STATUS 0x44 + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 +#define AR71XX_SPI_REG_CTRL 0x04 +#define AR71XX_SPI_REG_IOC 0x08 +#define AR71XX_SPI_REG_RDS 0x0c + +#define AR71XX_SPI_FS_GPIO BIT(0) + +#define AR71XX_SPI_CTRL_RD BIT(6) +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) +#define AR71XX_SPI_IOC_CLK BIT(8) +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL \ + (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 +#define AR933X_GPIO_REG_FUNC 0x30 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA953X_GPIO_REG_FUNC 0x6c + +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 +#define QCA956X_GPIO_REG_FUNC 0x6c + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO(x) BIT(x) +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_RES_TRUE BIT(15) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +#define AR934X_GPIO_OUT_GPIO 0 +#define AR934X_GPIO_OUT_SPI_CS1 7 +#define AR934X_GPIO_OUT_LED_LINK0 41 +#define AR934X_GPIO_OUT_LED_LINK1 42 +#define AR934X_GPIO_OUT_LED_LINK2 43 +#define AR934X_GPIO_OUT_LED_LINK3 44 +#define AR934X_GPIO_OUT_LED_LINK4 45 +#define AR934X_GPIO_OUT_EXT_LNA0 46 +#define AR934X_GPIO_OUT_EXT_LNA1 47 + +#define QCA953X_GPIO(x) BIT(x) +#define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 +#define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + +#define QCA953X_GPIO_IN_MUX_UART0_SIN 9 +#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 + +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 + +#define AR71XX_GPIO_COUNT 16 +#define AR7240_GPIO_COUNT 18 +#define AR7241_GPIO_COUNT 20 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA953X_GPIO_COUNT 18 +#define QCA955X_GPIO_COUNT 24 +#define QCA956X_GPIO_COUNT 23 + +/* + * SRIF block + */ +#define AR933X_SRIF_DDR_DPLL1_REG 0x240 +#define AR933X_SRIF_DDR_DPLL2_REG 0x244 +#define AR933X_SRIF_DDR_DPLL3_REG 0x248 +#define AR933X_SRIF_DDR_DPLL4_REG 0x24c + +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 +#define AR934X_SRIF_CPU_DPLL4_REG 0x1cc + +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 +#define AR934X_SRIF_DDR_DPLL4_REG 0x24c + +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define QCA953X_SRIF_BB_DPLL1_REG 0x180 +#define QCA953X_SRIF_BB_DPLL2_REG 0x184 +#define QCA953X_SRIF_BB_DPLL3_REG 0x188 + +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 + +#define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 +#define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 +#define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 + +#define QCA953X_SRIF_PMU1_REG 0xc40 +#define QCA953X_SRIF_PMU2_REG 0xc44 + +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f + +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) + +#define QCA953X_SRIF_DPLL2_KI_SHIFT 29 +#define QCA953X_SRIF_DPLL2_KI_MASK 0x3 + +#define QCA953X_SRIF_DPLL2_KD_SHIFT 25 +#define QCA953X_SRIF_DPLL2_KD_MASK 0xf + +#define QCA953X_SRIF_DPLL2_PWD BIT(22) + +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +/* + * MII_CTRL block + */ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* + * AR933X GMAC interface + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* + * AR934X GMAC Interface + */ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define AR934X_ETH_CFG_RXD_DELAY BIT(14) +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16) +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 + +/* + * QCA953X GMAC Interface + */ +#define QCA953X_GMAC_REG_ETH_CFG 0x00 + +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* + * QCA955X GMAC Interface + */ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) + +#endif /* __ASM_AR71XX_H */ diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h new file mode 100644 index 0000000..17af082 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -0,0 +1,149 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include <linux/types.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum ath79_soc_type { + ATH79_SOC_UNKNOWN, + ATH79_SOC_AR7130, + ATH79_SOC_AR7141, + ATH79_SOC_AR7161, + ATH79_SOC_AR7240, + ATH79_SOC_AR7241, + ATH79_SOC_AR7242, + ATH79_SOC_AR9130, + ATH79_SOC_AR9132, + ATH79_SOC_AR9330, + ATH79_SOC_AR9331, + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, + ATH79_SOC_QCA9533, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, + ATH79_SOC_TP9343, + ATH79_SOC_QCA9561, +}; + +static inline int soc_is_ar71xx(void) +{ + return gd->arch.soc == ATH79_SOC_AR7130 || + gd->arch.soc == ATH79_SOC_AR7141 || + gd->arch.soc == ATH79_SOC_AR7161; +} + +static inline int soc_is_ar724x(void) +{ + return gd->arch.soc == ATH79_SOC_AR7240 || + gd->arch.soc == ATH79_SOC_AR7241 || + gd->arch.soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar7240(void) +{ + return gd->arch.soc == ATH79_SOC_AR7240; +} + +static inline int soc_is_ar7241(void) +{ + return gd->arch.soc == ATH79_SOC_AR7241; +} + +static inline int soc_is_ar7242(void) +{ + return gd->arch.soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar913x(void) +{ + return gd->arch.soc == ATH79_SOC_AR9130 || + gd->arch.soc == ATH79_SOC_AR9132; +} + +static inline int soc_is_ar933x(void) +{ + return gd->arch.soc == ATH79_SOC_AR9330 || + gd->arch.soc == ATH79_SOC_AR9331; +} + +static inline int soc_is_ar9341(void) +{ + return gd->arch.soc == ATH79_SOC_AR9341; +} + +static inline int soc_is_ar9342(void) +{ + return gd->arch.soc == ATH79_SOC_AR9342; +} + +static inline int soc_is_ar9344(void) +{ + return gd->arch.soc == ATH79_SOC_AR9344; +} + +static inline int soc_is_ar934x(void) +{ + return soc_is_ar9341() || + soc_is_ar9342() || + soc_is_ar9344(); +} + +static inline int soc_is_qca9533(void) +{ + return gd->arch.soc == ATH79_SOC_QCA9533; +} + +static inline int soc_is_qca953x(void) +{ + return soc_is_qca9533(); +} + +static inline int soc_is_qca9556(void) +{ + return gd->arch.soc == ATH79_SOC_QCA9556; +} + +static inline int soc_is_qca9558(void) +{ + return gd->arch.soc == ATH79_SOC_QCA9558; +} + +static inline int soc_is_qca955x(void) +{ + return soc_is_qca9556() || soc_is_qca9558(); +} + +static inline int soc_is_tp9343(void) +{ + return gd->arch.soc == ATH79_SOC_TP9343; +} + +static inline int soc_is_qca9561(void) +{ + return gd->arch.soc == ATH79_SOC_QCA9561; +} + +static inline int soc_is_qca956x(void) +{ + return soc_is_tp9343() || soc_is_qca9561(); +} + +int ath79_eth_reset(void); +int ath79_usb_reset(void); + +void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz); +void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz); + +#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/include/mach/ddr.h b/arch/mips/mach-ath79/include/mach/ddr.h new file mode 100644 index 0000000..181179a --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ddr.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_DDR_H +#define __ASM_MACH_DDR_H + +void ddr_init(void); +void ddr_tap_tuning(void); + +#endif /* __ASM_MACH_DDR_H */ diff --git a/arch/mips/mach-ath79/include/mach/reset.h b/arch/mips/mach-ath79/include/mach/reset.h new file mode 100644 index 0000000..c383bfe --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/reset.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_RESET_H +#define __ASM_MACH_RESET_H + +#include <linux/types.h> + +u32 get_bootstrap(void); + +#endif /* __ASM_MACH_RESET_H */ diff --git a/arch/mips/mach-ath79/qca953x/Makefile b/arch/mips/mach-ath79/qca953x/Makefile new file mode 100644 index 0000000..fd74f0c --- /dev/null +++ b/arch/mips/mach-ath79/qca953x/Makefile @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk.o +obj-y += ddr.o +obj-y += lowlevel_init.o diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c new file mode 100644 index 0000000..ef0a28e --- /dev/null +++ b/arch/mips/mach-ath79/qca953x/clk.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +static u32 qca953x_get_xtal(void) +{ + u32 val; + + val = get_bootstrap(); + if (val & QCA953X_BOOTSTRAP_REF_CLK_40) + return 40000000; + else + return 25000000; +} + +int get_serial_clock(void) +{ + return qca953x_get_xtal(); +} + +int get_clocks(void) +{ + void __iomem *regs; + u32 val, ctrl, xtal, pll, div; + + regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, + MAP_NOCACHE); + + xtal = qca953x_get_xtal(); + ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG); + val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG); + + /* VCOOUT = XTAL * DIV_INT */ + div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) + & QCA953X_PLL_CPU_CONFIG_REFDIV_MASK; + pll = xtal / div; + + /* PLLOUT = VCOOUT * (1/2^OUTDIV) */ + div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) + & QCA953X_PLL_CPU_CONFIG_NINT_MASK; + pll *= div; + div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) + & QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; + if (!div) + div = 1; + pll >>= div; + + /* CPU_CLK = PLLOUT / CPU_POST_DIV */ + div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) + & QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1; + gd->cpu_clk = pll / div; + + + val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG); + /* VCOOUT = XTAL * DIV_INT */ + div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) + & QCA953X_PLL_DDR_CONFIG_REFDIV_MASK; + pll = xtal / div; + + /* PLLOUT = VCOOUT * (1/2^OUTDIV) */ + div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) + & QCA953X_PLL_DDR_CONFIG_NINT_MASK; + pll *= div; + div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) + & QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; + if (!div) + div = 1; + pll >>= div; + + /* DDR_CLK = PLLOUT / DDR_POST_DIV */ + div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) + & QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1; + gd->mem_clk = pll / div; + + div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) + & QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1; + if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) { + /* AHB_CLK = DDR_CLK / AHB_POST_DIV */ + gd->bus_clk = gd->mem_clk / (div + 1); + } else { + /* AHB_CLK = CPU_CLK / AHB_POST_DIV */ + gd->bus_clk = gd->cpu_clk / (div + 1); + } + + return 0; +} + +ulong get_bus_freq(ulong dummy) +{ + if (!gd->bus_clk) + get_clocks(); + return gd->bus_clk; +} + +ulong get_ddr_freq(ulong dummy) +{ + if (!gd->mem_clk) + get_clocks(); + return gd->mem_clk; +} diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c new file mode 100644 index 0000000..ac0130c --- /dev/null +++ b/arch/mips/mach-ath79/qca953x/ddr.c @@ -0,0 +1,472 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * Based on Atheros LSDK/QSDK + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DDR_CTRL_UPD_EMR3S BIT(5) +#define DDR_CTRL_UPD_EMR2S BIT(4) +#define DDR_CTRL_PRECHARGE BIT(3) +#define DDR_CTRL_AUTO_REFRESH BIT(2) +#define DDR_CTRL_UPD_EMRS BIT(1) +#define DDR_CTRL_UPD_MRS BIT(0) + +#define DDR_REFRESH_EN BIT(14) +#define DDR_REFRESH_M 0x3ff +#define DDR_REFRESH(x) ((x) & DDR_REFRESH_M) +#define DDR_REFRESH_VAL (DDR_REFRESH_EN | DDR_REFRESH(312)) + +#define DDR_TRAS_S 0 +#define DDR_TRAS_M 0x1f +#define DDR_TRAS(x) (((x) & DDR_TRAS_M) << DDR_TRAS_S) +#define DDR_TRCD_M 0xf +#define DDR_TRCD_S 5 +#define DDR_TRCD(x) (((x) & DDR_TRCD_M) << DDR_TRCD_S) +#define DDR_TRP_M 0xf +#define DDR_TRP_S 9 +#define DDR_TRP(x) (((x) & DDR_TRP_M) << DDR_TRP_S) +#define DDR_TRRD_M 0xf +#define DDR_TRRD_S 13 +#define DDR_TRRD(x) (((x) & DDR_TRRD_M) << DDR_TRRD_S) +#define DDR_TRFC_M 0x7f +#define DDR_TRFC_S 17 +#define DDR_TRFC(x) (((x) & DDR_TRFC_M) << DDR_TRFC_S) +#define DDR_TMRD_M 0xf +#define DDR_TMRD_S 23 +#define DDR_TMRD(x) (((x) & DDR_TMRD_M) << DDR_TMRD_S) +#define DDR_CAS_L_M 0x17 +#define DDR_CAS_L_S 27 +#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S) +#define DDR_OPEN BIT(30) +#define DDR1_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \ + DDR_TRP(6) | DDR_TRRD(4) | \ + DDR_TRFC(7) | DDR_TMRD(5) | \ + DDR_CAS_L(7) | DDR_OPEN) +#define DDR2_CONF_REG_VAL (DDR_TRAS(27) | DDR_TRCD(9) | \ + DDR_TRP(9) | DDR_TRRD(7) | \ + DDR_TRFC(21) | DDR_TMRD(15) | \ + DDR_CAS_L(17) | DDR_OPEN) + +#define DDR_BURST_LEN_S 0 +#define DDR_BURST_LEN_M 0xf +#define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S) +#define DDR_BURST_TYPE BIT(4) +#define DDR_CNTL_OE_EN BIT(5) +#define DDR_PHASE_SEL BIT(6) +#define DDR_CKE BIT(7) +#define DDR_TWR_S 8 +#define DDR_TWR_M 0xf +#define DDR_TWR(x) (((x) & DDR_TWR_M) << DDR_TWR_S) +#define DDR_TRTW_S 12 +#define DDR_TRTW_M 0x1f +#define DDR_TRTW(x) (((x) & DDR_TRTW_M) << DDR_TRTW_S) +#define DDR_TRTP_S 17 +#define DDR_TRTP_M 0xf +#define DDR_TRTP(x) (((x) & DDR_TRTP_M) << DDR_TRTP_S) +#define DDR_TWTR_S 21 +#define DDR_TWTR_M 0x1f +#define DDR_TWTR(x) (((x) & DDR_TWTR_M) << DDR_TWTR_S) +#define DDR_G_OPEN_L_S 26 +#define DDR_G_OPEN_L_M 0xf +#define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S) +#define DDR_HALF_WIDTH_LOW BIT(31) +#define DDR1_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \ + DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \ + DDR_TRTP(8) | DDR_TWTR(14) | \ + DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW) +#define DDR2_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \ + DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \ + DDR_TRTP(9) | DDR_TWTR(21) | \ + DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW) + +#define DDR_TWR_MSB BIT(3) +#define DDR_TRAS_MSB BIT(2) +#define DDR_TRFC_MSB_M 0x3 +#define DDR_TRFC_MSB(x) (x) +#define DDR1_CONF3_REG_VAL 0 +#define DDR2_CONF3_REG_VAL (DDR_TWR_MSB | DDR_TRFC_MSB(2)) + +#define DDR_CTL_SRAM_TSEL BIT(30) +#define DDR_CTL_SRAM_GE0_SYNC BIT(20) +#define DDR_CTL_SRAM_GE1_SYNC BIT(19) +#define DDR_CTL_SRAM_USB_SYNC BIT(18) +#define DDR_CTL_SRAM_PCIE_SYNC BIT(17) +#define DDR_CTL_SRAM_WMAC_SYNC BIT(16) +#define DDR_CTL_SRAM_MISC1_SYNC BIT(15) +#define DDR_CTL_SRAM_MISC2_SYNC BIT(14) +#define DDR_CTL_PAD_DDR2_SEL BIT(6) +#define DDR_CTL_HALF_WIDTH BIT(1) +#define DDR_CTL_CONFIG_VAL (DDR_CTL_SRAM_TSEL | \ + DDR_CTL_SRAM_GE0_SYNC | \ + DDR_CTL_SRAM_GE1_SYNC | \ + DDR_CTL_SRAM_USB_SYNC | \ + DDR_CTL_SRAM_PCIE_SYNC | \ + DDR_CTL_SRAM_WMAC_SYNC | \ + DDR_CTL_HALF_WIDTH) + +#define DDR_BURST_GE0_MAX_BL_S 0 +#define DDR_BURST_GE0_MAX_BL_M 0xf +#define DDR_BURST_GE0_MAX_BL(x) \ + (((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S) +#define DDR_BURST_GE1_MAX_BL_S 4 +#define DDR_BURST_GE1_MAX_BL_M 0xf +#define DDR_BURST_GE1_MAX_BL(x) \ + (((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S) +#define DDR_BURST_PCIE_MAX_BL_S 8 +#define DDR_BURST_PCIE_MAX_BL_M 0xf +#define DDR_BURST_PCIE_MAX_BL(x) \ + (((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S) +#define DDR_BURST_USB_MAX_BL_S 12 +#define DDR_BURST_USB_MAX_BL_M 0xf +#define DDR_BURST_USB_MAX_BL(x) \ + (((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S) +#define DDR_BURST_CPU_MAX_BL_S 16 +#define DDR_BURST_CPU_MAX_BL_M 0xf +#define DDR_BURST_CPU_MAX_BL(x) \ + (((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S) +#define DDR_BURST_RD_MAX_BL_S 20 +#define DDR_BURST_RD_MAX_BL_M 0xf +#define DDR_BURST_RD_MAX_BL(x) \ + (((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S) +#define DDR_BURST_WR_MAX_BL_S 24 +#define DDR_BURST_WR_MAX_BL_M 0xf +#define DDR_BURST_WR_MAX_BL(x) \ + (((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S) +#define DDR_BURST_RWP_MASK_EN_S 28 +#define DDR_BURST_RWP_MASK_EN_M 0x3 +#define DDR_BURST_RWP_MASK_EN(x) \ + (((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S) +#define DDR_BURST_CPU_PRI_BE BIT(30) +#define DDR_BURST_CPU_PRI BIT(31) +#define DDR_BURST_VAL (DDR_BURST_CPU_PRI_BE | \ + DDR_BURST_RWP_MASK_EN(3) | \ + DDR_BURST_WR_MAX_BL(4) | \ + DDR_BURST_RD_MAX_BL(4) | \ + DDR_BURST_CPU_MAX_BL(4) | \ + DDR_BURST_USB_MAX_BL(4) | \ + DDR_BURST_PCIE_MAX_BL(4) | \ + DDR_BURST_GE1_MAX_BL(4) | \ + DDR_BURST_GE0_MAX_BL(4)) + +#define DDR_BURST_WMAC_MAX_BL_S 0 +#define DDR_BURST_WMAC_MAX_BL_M 0xf +#define DDR_BURST_WMAC_MAX_BL(x) \ + (((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S) +#define DDR_BURST2_VAL DDR_BURST_WMAC_MAX_BL(4) + +#define DDR2_CONF_TWL_S 10 +#define DDR2_CONF_TWL_M 0xf +#define DDR2_CONF_TWL(x) \ + (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S) +#define DDR2_CONF_ODT BIT(9) +#define DDR2_CONF_TFAW_S 2 +#define DDR2_CONF_TFAW_M 0x3f +#define DDR2_CONF_TFAW(x) \ + (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S) +#define DDR2_CONF_EN BIT(0) +#define DDR2_CONF_VAL (DDR2_CONF_TWL(5) | \ + DDR2_CONF_TFAW(31) | \ + DDR2_CONF_ODT | \ + DDR2_CONF_EN) + +#define DDR1_EXT_MODE_VAL 0 +#define DDR2_EXT_MODE_VAL 0x402 +#define DDR2_EXT_MODE_OCD_VAL 0x782 +#define DDR1_MODE_DLL_VAL 0x133 +#define DDR2_MODE_DLL_VAL 0x143 +#define DDR1_MODE_VAL 0x33 +#define DDR2_MODE_VAL 0x43 +#define DDR1_TAP_VAL 0x20 +#define DDR2_TAP_VAL 0x10 + +#define DDR_REG_BIST_MASK_ADDR_0 0x2c +#define DDR_REG_BIST_MASK_ADDR_1 0x30 +#define DDR_REG_BIST_MASK_AHB_GE0_0 0x34 +#define DDR_REG_BIST_COMP_AHB_GE0_0 0x38 +#define DDR_REG_BIST_MASK_AHB_GE1_0 0x3c +#define DDR_REG_BIST_COMP_AHB_GE1_0 0x40 +#define DDR_REG_BIST_COMP_ADDR_0 0x64 +#define DDR_REG_BIST_COMP_ADDR_1 0x68 +#define DDR_REG_BIST_MASK_AHB_GE0_1 0x6c +#define DDR_REG_BIST_COMP_AHB_GE0_1 0x70 +#define DDR_REG_BIST_MASK_AHB_GE1_1 0x74 +#define DDR_REG_BIST_COMP_AHB_GE1_1 0x78 +#define DDR_REG_BIST 0x11c +#define DDR_REG_BIST_STATUS 0x120 + +#define DDR_BIST_COMP_CNT_S 1 +#define DDR_BIST_COMP_CNT_M 0xff +#define DDR_BIST_COMP_CNT(x) \ + (((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S) +#define DDR_BIST_COMP_CNT_MASK \ + (DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S) +#define DDR_BIST_TEST_START BIT(0) +#define DDR_BIST_STATUS_DONE BIT(0) + +/* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */ +#define DDR_BIST_MASK_ADDR_VAL 0xfa5de83f + +#define DDR_TAP_MAGIC_VAL 0xaa55aa55 +#define DDR_TAP_MAX_VAL 0x40 + +void ddr_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, + MAP_NOCACHE); + val = get_bootstrap(); + if (val & QCA953X_BOOTSTRAP_DDR1) { + writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF); + udelay(10); + + /* For 16-bit DDR */ + writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); + udelay(100); + + /* Burst size */ + writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST); + udelay(100); + writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2); + udelay(100); + + /* AHB maximum timeout */ + writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); + udelay(100); + + /* DRAM timing */ + writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); + udelay(100); + writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); + udelay(100); + writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); + udelay(100); + + /* Precharge All */ + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* ODT disable, Full strength, Enable DLL */ + writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); + udelay(100); + + /* Update Extended Mode Register Set (EMRS) */ + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Reset DLL, CAS Latency 3, Burst Length 8 */ + writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); + udelay(100); + + /* Update Mode Register Set (MRS) */ + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Precharge All */ + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Auto Refresh */ + writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Normal DLL, CAS Latency 3, Burst Length 8 */ + writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE); + udelay(100); + + /* Update Mode Register Set (MRS) */ + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Refresh time control */ + writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH); + udelay(100); + + /* DQS 0 Tap Control */ + writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); + + /* DQS 1 Tap Control */ + writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); + } else { + writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL, + regs + QCA953X_DDR_REG_CTL_CONF); + udelay(10); + + /* For 16-bit DDR */ + writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); + udelay(100); + + /* Burst size */ + writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST); + udelay(100); + writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2); + udelay(100); + + /* AHB maximum timeout */ + writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); + udelay(100); + + /* DRAM timing */ + writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); + udelay(100); + writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); + udelay(100); + writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); + udelay(100); + + /* Enable DDR2 */ + writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG); + udelay(100); + + /* Precharge All */ + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Update Extended Mode Register 2 Set (EMR2S) */ + writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Update Extended Mode Register 3 Set (EMR3S) */ + writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* 150 ohm, Reduced strength, Enable DLL */ + writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); + udelay(100); + + /* Update Extended Mode Register Set (EMRS) */ + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Reset DLL, CAS Latency 4, Burst Length 8 */ + writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); + udelay(100); + + /* Update Mode Register Set (MRS) */ + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Precharge All */ + writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Auto Refresh */ + writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Normal DLL, CAS Latency 4, Burst Length 8 */ + writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE); + udelay(100); + + /* Mode Register Set (MRS) */ + writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Enable OCD, Enable DLL, Reduced Drive Strength */ + writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR); + udelay(100); + + /* Update Extended Mode Register Set (EMRS) */ + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* OCD diable, Enable DLL, Reduced Drive Strength */ + writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); + udelay(100); + + /* Update Extended Mode Register Set (EMRS) */ + writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); + udelay(100); + + /* Refresh time control */ + writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH); + udelay(100); + + /* DQS 0 Tap Control */ + writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); + + /* DQS 1 Tap Control */ + writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); + } +} + +void ddr_tap_tuning(void) +{ + void __iomem *regs; + u32 val, pass, tap, cnt, tap_val, last, first; + + regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, + MAP_NOCACHE); + + tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); + first = DDR_TAP_MAGIC_VAL; + last = 0; + cnt = 0; + tap = 0; + + do { + writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0); + writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1); + + writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1); + writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0); + writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1); + writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0); + writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1); + writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0); + writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1); + writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0); + writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1); + writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0); + + /* Start BIST test */ + writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST); + + do { + val = readl(regs + DDR_REG_BIST_STATUS); + } while (!(val & DDR_BIST_STATUS_DONE)); + + /* Stop BIST test */ + writel(0, regs + DDR_REG_BIST); + + pass = val & DDR_BIST_COMP_CNT_MASK; + pass ^= DDR_BIST_COMP_CNT(8); + if (!pass) { + if (first != DDR_TAP_MAGIC_VAL) { + last = tap; + } else { + first = tap; + last = tap; + } + cnt++; + } + tap++; + } while (tap < DDR_TAP_MAX_VAL); + + if (cnt) { + tap_val = (first + last) / 2; + tap_val %= DDR_TAP_MAX_VAL; + } + + writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0); + writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1); +} diff --git a/arch/mips/mach-ath79/qca953x/lowlevel_init.S b/arch/mips/mach-ath79/qca953x/lowlevel_init.S new file mode 100644 index 0000000..d7038fa --- /dev/null +++ b/arch/mips/mach-ath79/qca953x/lowlevel_init.S @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * Based on Atheros LSDK/QSDK + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <mach/ar71xx_regs.h> + +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ + (((0x3F & divint) << 10) | \ + ((0x1F & refdiv) << 16) | \ + ((0x1 & range) << 21) | \ + ((0x7 & outdiv) << 23) ) + +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ + (((0x3 & (cpudiv - 1)) << 5) | \ + ((0x3 & (ddrdiv - 1)) << 10) | \ + ((0x3 & (ahbdiv - 1)) << 15) ) + +#define SET_FIELD(name, v) (((v) & QCA953X_##name##_MASK) << \ + QCA953X_##name##_SHIFT) + +#define DPLL2_KI(v) SET_FIELD(SRIF_DPLL2_KI, v) +#define DPLL2_KD(v) SET_FIELD(SRIF_DPLL2_KD, v) +#define DPLL2_PWD QCA953X_SRIF_DPLL2_PWD +#define MK_DPLL2(ki, kd) (DPLL2_KI(ki) | DPLL2_KD(kd) | DPLL2_PWD) + +#define PLL_CPU_NFRAC(v) SET_FIELD(PLL_CPU_CONFIG_NFRAC, v) +#define PLL_CPU_NINT(v) SET_FIELD(PLL_CPU_CONFIG_NINT, v) +#define PLL_CPU_REFDIV(v) SET_FIELD(PLL_CPU_CONFIG_REFDIV, v) +#define PLL_CPU_OUTDIV(v) SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v) +#define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \ + (PLL_CPU_NFRAC(frac) | \ + PLL_CPU_NINT(nint) | \ + PLL_CPU_REFDIV(ref) | \ + PLL_CPU_OUTDIV(outdiv)) + +#define PLL_DDR_NFRAC(v) SET_FIELD(PLL_DDR_CONFIG_NFRAC, v) +#define PLL_DDR_NINT(v) SET_FIELD(PLL_DDR_CONFIG_NINT, v) +#define PLL_DDR_REFDIV(v) SET_FIELD(PLL_DDR_CONFIG_REFDIV, v) +#define PLL_DDR_OUTDIV(v) SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v) +#define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \ + (PLL_DDR_NFRAC(frac) | \ + PLL_DDR_REFDIV(ref) | \ + PLL_DDR_NINT(nint) | \ + PLL_DDR_OUTDIV(outdiv) | \ + QCA953X_PLL_CONFIG_PWD) + +#define PLL_CPU_CONF_VAL MK_PLL_CPU_CONF(0, 26, 1, 0) +#define PLL_DDR_CONF_VAL MK_PLL_DDR_CONF(0, 15, 1, 0) + +#define PLL_CLK_CTRL_PLL_BYPASS (QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS | \ + QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS | \ + QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS) + +#define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v) +#define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v) +#define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v) +#define MK_PLL_CLK_CTRL(cpu, ddr, ahb) \ + (PLL_CLK_CTRL_CPU_DIV(cpu) | \ + PLL_CLK_CTRL_DDR_DIV(ddr) | \ + PLL_CLK_CTRL_AHB_DIV(ahb)) +#define PLL_CLK_CTRL_VAL (MK_PLL_CLK_CTRL(0, 0, 2) | \ + PLL_CLK_CTRL_PLL_BYPASS | \ + QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | \ + QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) + +#define PLL_DDR_DIT_FRAC_MAX(v) SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v) +#define PLL_DDR_DIT_FRAC_MIN(v) SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v) +#define PLL_DDR_DIT_FRAC_STEP(v) SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v) +#define PLL_DDR_DIT_UPD_CNT(v) SET_FIELD(PLL_DDR_DIT_UPD_CNT, v) +#define PLL_CPU_DIT_FRAC_MAX(v) SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v) +#define PLL_CPU_DIT_FRAC_MIN(v) SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v) +#define PLL_CPU_DIT_FRAC_STEP(v) SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v) +#define PLL_CPU_DIT_UPD_CNT(v) SET_FIELD(PLL_CPU_DIT_UPD_CNT, v) +#define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \ + (QCA953X_PLL_DIT_FRAC_EN | \ + PLL_DDR_DIT_FRAC_MAX(max) | \ + PLL_DDR_DIT_FRAC_MIN(min) | \ + PLL_DDR_DIT_FRAC_STEP(step) | \ + PLL_DDR_DIT_UPD_CNT(cnt)) +#define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \ + (QCA953X_PLL_DIT_FRAC_EN | \ + PLL_CPU_DIT_FRAC_MAX(max) | \ + PLL_CPU_DIT_FRAC_MIN(min) | \ + PLL_CPU_DIT_FRAC_STEP(step) | \ + PLL_CPU_DIT_UPD_CNT(cnt)) +#define PLL_CPU_DIT_FRAC_VAL MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15) +#define PLL_DDR_DIT_FRAC_VAL MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15) + + .text + .set noreorder + +LEAF(lowlevel_init) + /* RTC Reset */ + li t0, CKSEG1ADDR(AR71XX_RESET_BASE) + lw t1, QCA953X_RESET_REG_RESET_MODULE(t0) + li t2, 0x08000000 + or t1, t1, t2 + sw t1, QCA953X_RESET_REG_RESET_MODULE(t0) + nop + lw t1, QCA953X_RESET_REG_RESET_MODULE(t0) + li t2, 0xf7ffffff + and t1, t1, t2 + sw t1, QCA953X_RESET_REG_RESET_MODULE(t0) + nop + + /* RTC Force Wake */ + li t0, CKSEG1ADDR(QCA953X_RTC_BASE) + li t1, 0x01 + sw t1, QCA953X_RTC_REG_SYNC_RESET(t0) + nop + nop + + /* Wait for RTC in on state */ +1: + lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0) + andi t1, t1, 0x02 + beqz t1, 1b + nop + + li t0, CKSEG1ADDR(QCA953X_SRIF_BASE) + li t1, MK_DPLL2(2, 16) + sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0) + sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0) + sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0) + sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0) + + li t0, CKSEG1ADDR(AR71XX_PLL_BASE) + lw t1, QCA953X_PLL_CLK_CTRL_REG(t0) + ori t1, PLL_CLK_CTRL_PLL_BYPASS + sw t1, QCA953X_PLL_CLK_CTRL_REG(t0) + nop + + li t1, PLL_CPU_CONF_VAL + sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0) + nop + + li t1, PLL_DDR_CONF_VAL + sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0) + nop + + li t1, PLL_CLK_CTRL_VAL + sw t1, QCA953X_PLL_CLK_CTRL_REG(t0) + nop + + lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0) + li t2, ~QCA953X_PLL_CONFIG_PWD + and t1, t1, t2 + sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0) + nop + + lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0) + li t2, ~QCA953X_PLL_CONFIG_PWD + and t1, t1, t2 + sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0) + nop + + lw t1, QCA953X_PLL_CLK_CTRL_REG(t0) + li t2, ~PLL_CLK_CTRL_PLL_BYPASS + and t1, t1, t2 + sw t1, QCA953X_PLL_CLK_CTRL_REG(t0) + nop + + li t1, PLL_DDR_DIT_FRAC_VAL + sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0) + nop + + li t1, PLL_CPU_DIT_FRAC_VAL + sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0) + nop + + li t0, CKSEG1ADDR(AR71XX_RESET_BASE) + lui t1, 0x03fc + sw t1, 0xb4(t0) + + nop + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c new file mode 100644 index 0000000..188eccb --- /dev/null +++ b/arch/mips/mach-ath79/reset.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ath79.h> +#include <mach/ar71xx_regs.h> + +void _machine_restart(void) +{ + void __iomem *base; + u32 reg = 0; + + base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, + MAP_NOCACHE); + if (soc_is_ar71xx()) + reg = AR71XX_RESET_REG_RESET_MODULE; + else if (soc_is_ar724x()) + reg = AR724X_RESET_REG_RESET_MODULE; + else if (soc_is_ar913x()) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; + else if (soc_is_qca953x()) + reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else if (soc_is_qca956x()) + reg = QCA956X_RESET_REG_RESET_MODULE; + else + puts("Reset register not defined for this SOC\n"); + + if (reg) + setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP); + + while (1) + /* NOP */; +} + +u32 get_bootstrap(void) +{ + void __iomem *base; + u32 reg = 0; + + base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, + MAP_NOCACHE); + if (soc_is_ar933x()) + reg = AR933X_RESET_REG_BOOTSTRAP; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_BOOTSTRAP; + else if (soc_is_qca953x()) + reg = QCA953X_RESET_REG_BOOTSTRAP; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_BOOTSTRAP; + else if (soc_is_qca956x()) + reg = QCA956X_RESET_REG_BOOTSTRAP; + else + puts("Bootstrap register not defined for this SOC\n"); + + if (reg) + return readl(base + reg); + + return 0; +} + +static int eth_init_ar933x(void) +{ + void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, + MAP_NOCACHE); + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, + MAP_NOCACHE); + void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE, + MAP_NOCACHE); + const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | + AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO | + AR933X_RESET_ETH_SWITCH; + + /* Clear MDIO slave EN bit. */ + clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17)); + mdelay(10); + + /* Get Atheros S26 PHY out of reset. */ + clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG, + 0x1f, 0x10); + mdelay(10); + + setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask); + mdelay(10); + clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask); + mdelay(10); + + /* Configure AR93xx GMAC register. */ + clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG, + AR933X_ETH_CFG_MII_GE0_MASTER | + AR933X_ETH_CFG_MII_GE0_SLAVE, + AR933X_ETH_CFG_MII_GE0_SLAVE); + return 0; +} + +static int eth_init_ar934x(void) +{ + void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, + MAP_NOCACHE); + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, + MAP_NOCACHE); + void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE, + MAP_NOCACHE); + const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO | + AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO | + AR934X_RESET_ETH_SWITCH_ANALOG; + u32 reg; + + reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP); + if (reg & AR934X_BOOTSTRAP_REF_CLK_40) + writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + else + writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG); + + setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); + mdelay(1); + clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); + mdelay(1); + + /* Configure AR934x GMAC register. */ + writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG); + return 0; +} + +int ath79_eth_reset(void) +{ + /* + * Un-reset ethernet. DM still doesn't have any notion of reset + * framework, so we do it by hand here. + */ + if (soc_is_ar933x()) + return eth_init_ar933x(); + if (soc_is_ar934x()) + return eth_init_ar934x(); + + return -EINVAL; +} + +static int usb_reset_ar933x(void __iomem *reset_regs) +{ + /* Ungate the USB block */ + setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, + AR933X_RESET_USBSUS_OVERRIDE); + mdelay(1); + clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, + AR933X_RESET_USB_HOST); + mdelay(1); + clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, + AR933X_RESET_USB_PHY); + mdelay(1); + + return 0; +} + +static int usb_reset_ar934x(void __iomem *reset_regs) +{ + /* Ungate the USB block */ + setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, + AR934X_RESET_USBSUS_OVERRIDE); + mdelay(1); + clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, + AR934X_RESET_USB_PHY); + mdelay(1); + clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, + AR934X_RESET_USB_PHY_ANALOG); + mdelay(1); + clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, + AR934X_RESET_USB_HOST); + mdelay(1); + + return 0; +} + +int ath79_usb_reset(void) +{ + void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE, + AR71XX_USB_CTRL_SIZE, + MAP_NOCACHE); + void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE, + MAP_NOCACHE); + /* + * Turn on the Buff and Desc swap bits. + * NOTE: This write into an undocumented register in mandatory to + * get the USB controller operational in BigEndian mode. + */ + writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG); + + if (soc_is_ar933x()) + return usb_reset_ar933x(reset_regs); + if (soc_is_ar934x()) + return usb_reset_ar934x(reset_regs); + + return -EINVAL; +} |