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authorWills Wang <wills.wang@live.com>2016-05-30 22:54:50 +0800
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-05-31 10:17:54 +0200
commit375239174c6bc6a9966db333fa79f578154828f5 (patch)
tree4c69c15d8e5ab0b4a1ac24535646a608ac3b6f75 /arch/mips/mach-ath79/ar934x
parentd58de3157e3d04ebbf8e928cff9bfc2b3be22ad7 (diff)
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mips: ath79: Rename get_bootstrap into ath79_get_bootstrap
Add a platform prefix for function name in order to make more readable, and move it into ath79.h Signed-off-by: Wills Wang <wills.wang@live.com> Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/mips/mach-ath79/ar934x')
-rw-r--r--arch/mips/mach-ath79/ar934x/clk.c6
-rw-r--r--arch/mips/mach-ath79/ar934x/ddr.c4
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index 9c65184..9b41d3d 100644
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -9,7 +9,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -119,7 +119,7 @@ void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
/* Test for 40MHz XTAL */
- reg = get_bootstrap();
+ reg = ath79_get_bootstrap();
if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
xtal_40 = 1;
cpu_srif = 0x41c00000;
@@ -214,7 +214,7 @@ static u32 ar934x_get_xtal(void)
{
u32 val;
- val = get_bootstrap();
+ val = ath79_get_bootstrap();
if (val & AR934X_BOOTSTRAP_REF_CLK_40)
return 40000000;
else
diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c
index 4621d58..2ba1efa 100644
--- a/arch/mips/mach-ath79/ar934x/ddr.c
+++ b/arch/mips/mach-ath79/ar934x/ddr.c
@@ -11,7 +11,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -45,7 +45,7 @@ void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
- reg = get_bootstrap();
+ reg = ath79_get_bootstrap();
if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */
if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */
memtype = AR934X_DDR1;