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author | Xiangfu Liu <xiangfu@openmobilefree.net> | 2011-10-12 12:24:06 +0800 |
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committer | Shinya Kuribayashi <skuribay@pobox.com> | 2011-10-10 22:06:12 +0900 |
commit | 80421fcc3ed1843f62a4a463548a4f33cdde362f (patch) | |
tree | 0e17b489ca37e73be16fbc1f85fd8b8c63cb773b /arch/mips/cpu/xburst/cpu.c | |
parent | 0841ca90f22d73b0ea4642ef1ce33d879bb2f3ff (diff) | |
download | u-boot-imx-80421fcc3ed1843f62a4a463548a4f33cdde362f.zip u-boot-imx-80421fcc3ed1843f62a4a463548a4f33cdde362f.tar.gz u-boot-imx-80421fcc3ed1843f62a4a463548a4f33cdde362f.tar.bz2 |
MIPS: Ingenic XBurst Jz4740 processor support
Jz4740 is a multimedia application processor targeting for mobile
devices like e-Dictionary, eBook, portable media player (PMP) and
GPS navigator. Jz4740 is powered by Ingenic 360 MHz XBurst CPU core
(JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture
provides high integration, high performance and low power consumption.
JzRISC incorporated in Jz4740 is the advanced and power-efficient
32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K
D-Cache, and can operate at speeds up to 400 MHz.
On-chip modules such as LCD controller, embedded audio codec, multi-
channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich
suite of peripherals for multimedia application. NAND controller
(SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are
also available.
For more info about Ingenic XBurst Jz4740:
http://en.ingenic.cn/eng/
http://www.linux-mips.org/wiki/Ingenic
This patch introduces XBurst CPU support in U-Boot. It's compatible
with MIPS32, but requires a bit different cache maintenance, timer
routines, and boot mechanism using USB boot tool, so XBurst support
can go into a separate new home, cpu/xburst/.
Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Daniel <zpxu@ingenic.cn>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Diffstat (limited to 'arch/mips/cpu/xburst/cpu.c')
-rw-r--r-- | arch/mips/cpu/xburst/cpu.c | 152 |
1 files changed, 152 insertions, 0 deletions
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c new file mode 100644 index 0000000..e976341 --- /dev/null +++ b/arch/mips/cpu/xburst/cpu.c @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> + * (C) Copyright 2011 + * Xiangfu Liu <xiangfu@openmobilefree.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <asm/mipsregs.h> +#include <asm/cacheops.h> +#include <asm/reboot.h> +#include <asm/io.h> +#include <asm/jz4740.h> + +#define cache_op(op, addr) \ + __asm__ __volatile__( \ + ".set push\n" \ + ".set noreorder\n" \ + ".set mips3\n" \ + "cache %0, %1\n" \ + ".set pop\n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void __attribute__((weak)) _machine_restart(void) +{ + struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE; + struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE; + u16 tmp; + + /* wdt_select_extalclk() */ + tmp = readw(&wdt->tcsr); + tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN); + tmp |= WDT_TCSR_EXT_EN; + writew(tmp, &wdt->tcsr); + + /* wdt_select_clk_div64() */ + tmp = readw(&wdt->tcsr); + tmp &= ~WDT_TCSR_PRESCALE_MASK; + tmp |= WDT_TCSR_PRESCALE64, + writew(tmp, &wdt->tcsr); + + writew(100, &wdt->tdr); /* wdt_set_data(100) */ + writew(0, &wdt->tcnt); /* wdt_set_count(0); */ + writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */ + writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */ + + while (1) + ; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + _machine_restart(); + + fprintf(stderr, "*** reset failed ***\n"); + return 0; +} + +void flush_cache(ulong start_addr, ulong size) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + for (; addr <= aend; addr += lsize) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + } +} + +void flush_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + for (; addr <= aend; addr += lsize) + cache_op(Hit_Writeback_Inv_D, addr); +} + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + for (; addr <= aend; addr += lsize) + cache_op(Hit_Invalidate_D, addr); +} + +void flush_icache_all(void) +{ + u32 addr, t = 0; + + __asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */ + __asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */ + + for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + cache_op(Index_Store_Tag_I, addr); + } + + /* invalidate btb */ + __asm__ __volatile__( + ".set mips32\n\t" + "mfc0 %0, $16, 7\n\t" + "nop\n\t" + "ori %0,2\n\t" + "mtc0 %0, $16, 7\n\t" + ".set mips2\n\t" + : + : "r" (t)); +} + +void flush_dcache_all(void) +{ + u32 addr; + + for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + cache_op(Index_Writeback_Inv_D, addr); + } + + __asm__ __volatile__("sync"); +} + +void flush_cache_all(void) +{ + flush_dcache_all(); + flush_icache_all(); +} |