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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-06-13 12:59:27 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-07-24 09:51:05 -0400 |
| commit | 680cb2dc3a7ba1a9a5e8ca919d980e99906a767b (patch) | |
| tree | 5945bdf13774f71113de404c69875e0b5e733fd2 /arch/mips/cpu/mips32 | |
| parent | da84f33b046fe99c5fbb6f7d8f8b03c7333b260d (diff) | |
| download | u-boot-imx-680cb2dc3a7ba1a9a5e8ca919d980e99906a767b.zip u-boot-imx-680cb2dc3a7ba1a9a5e8ca919d980e99906a767b.tar.gz u-boot-imx-680cb2dc3a7ba1a9a5e8ca919d980e99906a767b.tar.bz2 | |
MIPS: mips32/start.S: use t8 register for dynamic relocation
Synchronize the code with mips64/start.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Diffstat (limited to 'arch/mips/cpu/mips32')
| -rw-r--r-- | arch/mips/cpu/mips32/start.S | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 2f1e486..f5ebe79 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -205,19 +205,19 @@ in_ram: * generated by GNU ld. Skip these reserved entries from relocation. */ lw t3, -4(t0) # t3 <-- num_got_entries - lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_ - add t4, s1 # t4 now holds relocated _G_O_T_ - addi t4, t4, 8 # skipping first two entries + lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + add t8, s1 # t8 now holds relocated _G_O_T_ + addi t8, t8, 8 # skipping first two entries li t2, 2 1: - lw t1, 0(t4) + lw t1, 0(t8) beqz t1, 2f add t1, s1 - sw t1, 0(t4) + sw t1, 0(t8) 2: addi t2, 1 blt t2, t3, 1b - addi t4, 4 + addi t8, 4 /* Update dynamic relocations */ lw t1, -16(t0) # t1 <-- __rel_dyn_start @@ -235,11 +235,11 @@ in_ram: lw t3, -8(t1) # t3 <-- location to fix up in FLASH - lw t4, 0(t3) # t4 <-- original pointer - add t4, s1 # t4 <-- adjusted pointer + lw t8, 0(t3) # t8 <-- original pointer + add t8, s1 # t8 <-- adjusted pointer add t3, s1 # t3 <-- location to fix up in RAM - sw t4, 0(t3) + sw t8, 0(t3) 2: blt t1, t2, 1b |