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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-06-23 12:18:44 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-07-14 18:03:16 -0600 |
| commit | d402f922b291bb76e7e3b5c15dda7abf1ce33b85 (patch) | |
| tree | 32c5e277af075bbb0a996f2416e385ee348527f0 /arch/mips/cpu/cpu.c | |
| parent | b0014b6423574780cdcb9a76478be0c1f83f7990 (diff) | |
| download | u-boot-imx-d402f922b291bb76e7e3b5c15dda7abf1ce33b85.zip u-boot-imx-d402f922b291bb76e7e3b5c15dda7abf1ce33b85.tar.gz u-boot-imx-d402f922b291bb76e7e3b5c15dda7abf1ce33b85.tar.bz2 | |
x86: queensbay: Correct Topcliff device irqs
There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.
This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/mips/cpu/cpu.c')
0 files changed, 0 insertions, 0 deletions