summaryrefslogtreecommitdiff
path: root/arch/m68k/include/asm/coldfire
diff options
context:
space:
mode:
authorPeter Tyser <ptyser@xes-inc.com>2010-04-12 22:28:08 -0500
committerWolfgang Denk <wd@denx.de>2010-04-13 09:13:12 +0200
commit819833af39a91fa1c1e8252862bbda6f5a602f7b (patch)
treed5c9d1628643347ab2b5a8085acfa6f96709fda3 /arch/m68k/include/asm/coldfire
parent61f2b38a17f5b21c59f2afe6cf1cbb5f28638cf9 (diff)
downloadu-boot-imx-819833af39a91fa1c1e8252862bbda6f5a602f7b.zip
u-boot-imx-819833af39a91fa1c1e8252862bbda6f5a602f7b.tar.gz
u-boot-imx-819833af39a91fa1c1e8252862bbda6f5a602f7b.tar.bz2
Move architecture-specific includes to arch/$ARCH/include/asm
This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'arch/m68k/include/asm/coldfire')
-rw-r--r--arch/m68k/include/asm/coldfire/ata.h79
-rw-r--r--arch/m68k/include/asm/coldfire/crossbar.h79
-rw-r--r--arch/m68k/include/asm/coldfire/dspi.h158
-rw-r--r--arch/m68k/include/asm/coldfire/edma.h177
-rw-r--r--arch/m68k/include/asm/coldfire/eport.h139
-rw-r--r--arch/m68k/include/asm/coldfire/flexbus.h120
-rw-r--r--arch/m68k/include/asm/coldfire/flexcan.h219
-rw-r--r--arch/m68k/include/asm/coldfire/intctrl.h246
-rw-r--r--arch/m68k/include/asm/coldfire/lcd.h213
-rw-r--r--arch/m68k/include/asm/coldfire/mdha.h102
-rw-r--r--arch/m68k/include/asm/coldfire/pwm.h115
-rw-r--r--arch/m68k/include/asm/coldfire/qspi.h111
-rw-r--r--arch/m68k/include/asm/coldfire/rng.h52
-rw-r--r--arch/m68k/include/asm/coldfire/skha.h121
-rw-r--r--arch/m68k/include/asm/coldfire/ssi.h169
15 files changed, 2100 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/coldfire/ata.h b/arch/m68k/include/asm/coldfire/ata.h
new file mode 100644
index 0000000..3efd03a
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/ata.h
@@ -0,0 +1,79 @@
+/*
+ * ATA Internal Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ATA_H__
+#define __ATA_H__
+
+/* ATA */
+typedef struct atac {
+ /* PIO */
+ u8 toff; /* 0x00 */
+ u8 ton; /* 0x01 */
+ u8 t1; /* 0x02 */
+ u8 t2w; /* 0x03 */
+ u8 t2r; /* 0x04 */
+ u8 ta; /* 0x05 */
+ u8 trd; /* 0x06 */
+ u8 t4; /* 0x07 */
+ u8 t9; /* 0x08 */
+
+ /* DMA */
+ u8 tm; /* 0x09 */
+ u8 tn; /* 0x0A */
+ u8 td; /* 0x0B */
+ u8 tk; /* 0x0C */
+ u8 tack; /* 0x0D */
+ u8 tenv; /* 0x0E */
+ u8 trp; /* 0x0F */
+ u8 tzah; /* 0x10 */
+ u8 tmli; /* 0x11 */
+ u8 tdvh; /* 0x12 */
+ u8 tdzfs; /* 0x13 */
+ u8 tdvs; /* 0x14 */
+ u8 tcvh; /* 0x15 */
+ u8 tss; /* 0x16 */
+ u8 tcyc; /* 0x17 */
+
+ /* FIFO */
+ u32 fifo32; /* 0x18 */
+ u16 fifo16; /* 0x1C */
+ u8 rsvd0[2];
+ u8 ffill; /* 0x20 */
+ u8 rsvd1[3];
+
+ /* ATA */
+ u8 cr; /* 0x24 */
+ u8 rsvd2[3];
+ u8 isr; /* 0x28 */
+ u8 rsvd3[3];
+ u8 ier; /* 0x2C */
+ u8 rsvd4[3];
+ u8 icr; /* 0x30 */
+ u8 rsvd5[3];
+ u8 falarm; /* 0x34 */
+ u8 rsvd6[106];
+} atac_t;
+
+#endif /* __ATA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/crossbar.h b/arch/m68k/include/asm/coldfire/crossbar.h
new file mode 100644
index 0000000..a9c724c
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/crossbar.h
@@ -0,0 +1,79 @@
+/*
+ * Cross Bar Switch Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CROSSBAR_H__
+#define __CROSSBAR_H__
+
+/*********************************************************************
+* Cross-bar switch (XBS)
+*********************************************************************/
+typedef struct xbs {
+ u32 prs1; /* 0x100 Priority Register Slave 1 */
+ u32 res1[3]; /* 0x104 - 0F */
+ u32 crs1; /* 0x110 Control Register Slave 1 */
+ u32 res2[187]; /* 0x114 - 0x3FF */
+
+ u32 prs4; /* 0x400 Priority Register Slave 4 */
+ u32 res3[3]; /* 0x404 - 0F */
+ u32 crs4; /* 0x410 Control Register Slave 4 */
+ u32 res4[123]; /* 0x414 - 0x5FF */
+
+ u32 prs6; /* 0x600 Priority Register Slave 6 */
+ u32 res5[3]; /* 0x604 - 0F */
+ u32 crs6; /* 0x610 Control Register Slave 6 */
+ u32 res6[59]; /* 0x614 - 0x6FF */
+
+ u32 prs7; /* 0x700 Priority Register Slave 7 */
+ u32 res7[3]; /* 0x704 - 0F */
+ u32 crs7; /* 0x710 Control Register Slave 7 */
+} xbs_t;
+
+/* Bit definitions and macros for PRS group */
+#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
+#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
+#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
+#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
+#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
+#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
+#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
+
+/* Bit definitions and macros for CRS group */
+#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
+#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
+#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
+#define XBS_CRS_RO (0x80000000) /* Read Only */
+
+#define XBS_CRS_PCTL_PARK_FIELD (0)
+#define XBS_CRS_PCTL_PARK_ON_LAST (1)
+#define XBS_CRS_PCTL_PARK_NONE (2)
+#define XBS_CRS_PCTL_PARK_CORE (0)
+#define XBS_CRS_PCTL_PARK_EDMA (1)
+#define XBS_CRS_PCTL_PARK_FEC0 (2)
+#define XBS_CRS_PCTL_PARK_FEC1 (3)
+#define XBS_CRS_PCTL_PARK_PCI (5)
+#define XBS_CRS_PCTL_PARK_USB (6)
+#define XBS_CRS_PCTL_PARK_SBF (7)
+
+#endif /* __CROSSBAR_H__ */
diff --git a/arch/m68k/include/asm/coldfire/dspi.h b/arch/m68k/include/asm/coldfire/dspi.h
new file mode 100644
index 0000000..02d1409
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/dspi.h
@@ -0,0 +1,158 @@
+/*
+ * MCF5227x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DSPI_H__
+#define __DSPI_H__
+
+/* DMA Serial Peripheral Interface (DSPI) */
+typedef struct dspi {
+ u32 mcr; /* 0x00 */
+ u32 resv0; /* 0x04 */
+ u32 tcr; /* 0x08 */
+ u32 ctar[8]; /* 0x0C - 0x28 */
+ u32 sr; /* 0x2C */
+ u32 irsr; /* 0x30 */
+ u32 tfr; /* 0x34 - PUSHR */
+ u16 resv1; /* 0x38 */
+ u16 rfr; /* 0x3A - POPR */
+#ifdef CONFIG_MCF547x_8x
+ u32 tfdr[4]; /* 0x3C */
+ u8 resv2[0x30]; /* 0x40 */
+ u32 rfdr[4]; /* 0x7C */
+#else
+ u32 tfdr[16]; /* 0x3C */
+ u32 rfdr[16]; /* 0x7C */
+#endif
+} dspi_t;
+
+/* Module configuration */
+#define DSPI_MCR_MSTR (0x80000000)
+#define DSPI_MCR_CSCK (0x40000000)
+#define DSPI_MCR_DCONF(x) (((x)&0x03)<<28)
+#define DSPI_MCR_FRZ (0x08000000)
+#define DSPI_MCR_MTFE (0x04000000)
+#define DSPI_MCR_PCSSE (0x02000000)
+#define DSPI_MCR_ROOE (0x01000000)
+#define DSPI_MCR_CSIS7 (0x00800000)
+#define DSPI_MCR_CSIS6 (0x00400000)
+#define DSPI_MCR_CSIS5 (0x00200000)
+#define DSPI_MCR_CSIS4 (0x00100000)
+#define DSPI_MCR_CSIS3 (0x00080000)
+#define DSPI_MCR_CSIS2 (0x00040000)
+#define DSPI_MCR_CSIS1 (0x00020000)
+#define DSPI_MCR_CSIS0 (0x00010000)
+#define DSPI_MCR_MDIS (0x00004000)
+#define DSPI_MCR_DTXF (0x00002000)
+#define DSPI_MCR_DRXF (0x00001000)
+#define DSPI_MCR_CTXF (0x00000800)
+#define DSPI_MCR_CRXF (0x00000400)
+#define DSPI_MCR_SMPL_PT(x) (((x)&0x03)<<8)
+#define DSPI_MCR_HALT (0x00000001)
+
+/* Transfer count */
+#define DSPI_TCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
+
+/* Clock and transfer attributes */
+#define DSPI_CTAR_DBR (0x80000000)
+#define DSPI_CTAR_TRSZ(x) (((x)&0x0F)<<27)
+#define DSPI_CTAR_CPOL (0x04000000)
+#define DSPI_CTAR_CPHA (0x02000000)
+#define DSPI_CTAR_LSBFE (0x01000000)
+#define DSPI_CTAR_PCSSCK(x) (((x)&0x03)<<22)
+#define DSPI_CTAR_PCSSCK_7CLK (0x00A00000)
+#define DSPI_CTAR_PCSSCK_5CLK (0x00800000)
+#define DSPI_CTAR_PCSSCK_3CLK (0x00400000)
+#define DSPI_CTAR_PCSSCK_1CLK (0x00000000)
+#define DSPI_CTAR_PASC(x) (((x)&0x03)<<20)
+#define DSPI_CTAR_PASC_7CLK (0x00300000)
+#define DSPI_CTAR_PASC_5CLK (0x00200000)
+#define DSPI_CTAR_PASC_3CLK (0x00100000)
+#define DSPI_CTAR_PASC_1CLK (0x00000000)
+#define DSPI_CTAR_PDT(x) (((x)&0x03)<<18)
+#define DSPI_CTAR_PDT_7CLK (0x000A0000)
+#define DSPI_CTAR_PDT_5CLK (0x00080000)
+#define DSPI_CTAR_PDT_3CLK (0x00040000)
+#define DSPI_CTAR_PDT_1CLK (0x00000000)
+#define DSPI_CTAR_PBR(x) (((x)&0x03)<<16)
+#define DSPI_CTAR_PBR_7CLK (0x00030000)
+#define DSPI_CTAR_PBR_5CLK (0x00020000)
+#define DSPI_CTAR_PBR_3CLK (0x00010000)
+#define DSPI_CTAR_PBR_1CLK (0x00000000)
+#define DSPI_CTAR_CSSCK(x) (((x)&0x0F)<<12)
+#define DSPI_CTAR_ASC(x) (((x)&0x0F)<<8)
+#define DSPI_CTAR_DT(x) (((x)&0x0F)<<4)
+#define DSPI_CTAR_BR(x) (((x)&0x0F))
+
+/* Status */
+#define DSPI_SR_TCF (0x80000000)
+#define DSPI_SR_TXRXS (0x40000000)
+#define DSPI_SR_EOQF (0x10000000)
+#define DSPI_SR_TFUF (0x08000000)
+#define DSPI_SR_TFFF (0x02000000)
+#define DSPI_SR_RFOF (0x00080000)
+#define DSPI_SR_RFDF (0x00020000)
+#define DSPI_SR_TXCTR(x) (((x)&0x0F)<<12)
+#define DSPI_SR_TXPTR(x) (((x)&0x0F)<<8)
+#define DSPI_SR_RXCTR(x) (((x)&0x0F)<<4)
+#define DSPI_SR_RXPTR(x) (((x)&0x0F))
+
+/* DMA/interrupt request selct and enable */
+#define DSPI_IRSR_TCFE (0x80000000)
+#define DSPI_IRSR_EOQFE (0x10000000)
+#define DSPI_IRSR_TFUFE (0x08000000)
+#define DSPI_IRSR_TFFFE (0x02000000)
+#define DSPI_IRSR_TFFFS (0x01000000)
+#define DSPI_IRSR_RFOFE (0x00080000)
+#define DSPI_IRSR_RFDFE (0x00020000)
+#define DSPI_IRSR_RFDFS (0x00010000)
+
+/* Transfer control - 32-bit access */
+#define DSPI_TFR_CONT (0x80000000)
+#define DSPI_TFR_CTAS(x) (((x)&0x07)<<12)
+#define DSPI_TFR_EOQ (0x08000000)
+#define DSPI_TFR_CTCNT (0x04000000)
+#define DSPI_TFR_CS7 (0x00800000)
+#define DSPI_TFR_CS6 (0x00400000)
+#define DSPI_TFR_CS5 (0x00200000)
+#define DSPI_TFR_CS4 (0x00100000)
+#define DSPI_TFR_CS3 (0x00080000)
+#define DSPI_TFR_CS2 (0x00040000)
+#define DSPI_TFR_CS1 (0x00020000)
+#define DSPI_TFR_CS0 (0x00010000)
+
+/* Transfer Fifo */
+#define DSPI_TFR_TXDATA(x) (((x)&0xFFFF))
+
+/* Bit definitions and macros for DRFR */
+#define DSPI_RFR_RXDATA(x) (((x)&0xFFFF))
+
+/* Bit definitions and macros for DTFDR group */
+#define DSPI_TFDR_TXDATA(x) (((x)&0x0000FFFF))
+#define DSPI_TFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for DRFDR group */
+#define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF))
+
+#endif /* __DSPI_H__ */
diff --git a/arch/m68k/include/asm/coldfire/edma.h b/arch/m68k/include/asm/coldfire/edma.h
new file mode 100644
index 0000000..c88aea6
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/edma.h
@@ -0,0 +1,177 @@
+/*
+ * EDMA Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EDMA_H__
+#define __EDMA_H__
+
+/*********************************************************************
+* Enhanced DMA (EDMA)
+*********************************************************************/
+
+/* eDMA module registers */
+typedef struct edma_ctrl {
+ u32 cr; /* 0x00 Control Register */
+ u32 es; /* 0x04 Error Status Register */
+ u16 res1[3]; /* 0x08 - 0x0D */
+ u16 erq; /* 0x0E Enable Request Register */
+ u16 res2[3]; /* 0x10 - 0x15 */
+ u16 eei; /* 0x16 Enable Error Interrupt Request */
+ u8 serq; /* 0x18 Set Enable Request */
+ u8 cerq; /* 0x19 Clear Enable Request */
+ u8 seei; /* 0x1A Set En Error Interrupt Request */
+ u8 ceei; /* 0x1B Clear En Error Interrupt Request */
+ u8 cint; /* 0x1C Clear Interrupt Enable */
+ u8 cerr; /* 0x1D Clear Error */
+ u8 ssrt; /* 0x1E Set START Bit */
+ u8 cdne; /* 0x1F Clear DONE Status Bit */
+ u16 res3[3]; /* 0x20 - 0x25 */
+ u16 intr; /* 0x26 Interrupt Request */
+ u16 res4[3]; /* 0x28 - 0x2D */
+ u16 err; /* 0x2E Error Register */
+ u32 res5[52]; /* 0x30 - 0xFF */
+ u8 dchpri0; /* 0x100 Channel 0 Priority */
+ u8 dchpri1; /* 0x101 Channel 1 Priority */
+ u8 dchpri2; /* 0x102 Channel 2 Priority */
+ u8 dchpri3; /* 0x103 Channel 3 Priority */
+ u8 dchpri4; /* 0x104 Channel 4 Priority */
+ u8 dchpri5; /* 0x105 Channel 5 Priority */
+ u8 dchpri6; /* 0x106 Channel 6 Priority */
+ u8 dchpri7; /* 0x107 Channel 7 Priority */
+ u8 dchpri8; /* 0x108 Channel 8 Priority */
+ u8 dchpri9; /* 0x109 Channel 9 Priority */
+ u8 dchpri10; /* 0x110 Channel 10 Priority */
+ u8 dchpri11; /* 0x111 Channel 11 Priority */
+ u8 dchpri12; /* 0x112 Channel 12 Priority */
+ u8 dchpri13; /* 0x113 Channel 13 Priority */
+ u8 dchpri14; /* 0x114 Channel 14 Priority */
+ u8 dchpri15; /* 0x115 Channel 15 Priority */
+} edma_t;
+
+/* TCD - eDMA*/
+typedef struct tcd_ctrl {
+ u32 saddr; /* 0x00 Source Address */
+ u16 attr; /* 0x04 Transfer Attributes */
+ u16 soff; /* 0x06 Signed Source Address Offset */
+ u32 nbytes; /* 0x08 Minor Byte Count */
+ u32 slast; /* 0x0C Last Source Address Adjustment */
+ u32 daddr; /* 0x10 Destination address */
+ u16 citer; /* 0x14 Cur Minor Loop Link, Major Loop Cnt */
+ u16 doff; /* 0x16 Signed Destination Address Offset */
+ u32 dlast_sga; /* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
+ u16 biter; /* 0x1C Minor Loop Lnk, Major Loop Cnt */
+ u16 csr; /* 0x1E Control and Status */
+} tcd_st;
+
+typedef struct tcd_multiple {
+ tcd_st tcd[16];
+} tcd_t;
+
+/* Bit definitions and macros for EPPAR */
+#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
+#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
+#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
+#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
+#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
+#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
+#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
+#define EPORT_EPPAR_LEVEL (0)
+#define EPORT_EPPAR_RISING (1)
+#define EPORT_EPPAR_FALLING (2)
+#define EPORT_EPPAR_BOTH (3)
+#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA7_RISING (0x4000)
+#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
+#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
+#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA6_RISING (0x1000)
+#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
+#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
+#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA5_RISING (0x0400)
+#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
+#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
+#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA4_RISING (0x0100)
+#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
+#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
+#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA3_RISING (0x0040)
+#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
+#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
+#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA2_RISING (0x0010)
+#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
+#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
+#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
+#define EPORT_EPPAR_EPPA1_RISING (0x0004)
+#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
+#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
+
+/* Bit definitions and macros for EPDDR */
+#define EPORT_EPDDR_EPDD1 (0x02)
+#define EPORT_EPDDR_EPDD2 (0x04)
+#define EPORT_EPDDR_EPDD3 (0x08)
+#define EPORT_EPDDR_EPDD4 (0x10)
+#define EPORT_EPDDR_EPDD5 (0x20)
+#define EPORT_EPDDR_EPDD6 (0x40)
+#define EPORT_EPDDR_EPDD7 (0x80)
+
+/* Bit definitions and macros for EPIER */
+#define EPORT_EPIER_EPIE1 (0x02)
+#define EPORT_EPIER_EPIE2 (0x04)
+#define EPORT_EPIER_EPIE3 (0x08)
+#define EPORT_EPIER_EPIE4 (0x10)
+#define EPORT_EPIER_EPIE5 (0x20)
+#define EPORT_EPIER_EPIE6 (0x40)
+#define EPORT_EPIER_EPIE7 (0x80)
+
+/* Bit definitions and macros for EPDR */
+#define EPORT_EPDR_EPD1 (0x02)
+#define EPORT_EPDR_EPD2 (0x04)
+#define EPORT_EPDR_EPD3 (0x08)
+#define EPORT_EPDR_EPD4 (0x10)
+#define EPORT_EPDR_EPD5 (0x20)
+#define EPORT_EPDR_EPD6 (0x40)
+#define EPORT_EPDR_EPD7 (0x80)
+
+/* Bit definitions and macros for EPPDR */
+#define EPORT_EPPDR_EPPD1 (0x02)
+#define EPORT_EPPDR_EPPD2 (0x04)
+#define EPORT_EPPDR_EPPD3 (0x08)
+#define EPORT_EPPDR_EPPD4 (0x10)
+#define EPORT_EPPDR_EPPD5 (0x20)
+#define EPORT_EPPDR_EPPD6 (0x40)
+#define EPORT_EPPDR_EPPD7 (0x80)
+
+/* Bit definitions and macros for EPFR */
+#define EPORT_EPFR_EPF1 (0x02)
+#define EPORT_EPFR_EPF2 (0x04)
+#define EPORT_EPFR_EPF3 (0x08)
+#define EPORT_EPFR_EPF4 (0x10)
+#define EPORT_EPFR_EPF5 (0x20)
+#define EPORT_EPFR_EPF6 (0x40)
+#define EPORT_EPFR_EPF7 (0x80)
+
+#endif /* __EDMA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/eport.h b/arch/m68k/include/asm/coldfire/eport.h
new file mode 100644
index 0000000..1d1bf63
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/eport.h
@@ -0,0 +1,139 @@
+/*
+ * Edge Port Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EPORT_H__
+#define __EPORT_H__
+
+/* Edge Port Module (EPORT) */
+typedef struct eport {
+#ifdef CONFIG_MCF547x_8x
+ u16 par; /* 0x00 */
+ u16 res0; /* 0x02 */
+ u8 ddr; /* 0x04 */
+ u8 ier; /* 0x05 */
+ u16 res1; /* 0x06 */
+ u8 dr; /* 0x08 */
+ u8 pdr; /* 0x09 */
+ u16 res2; /* 0x0A */
+ u8 fr; /* 0x0C */
+ u8 res3[3]; /* 0x0D */
+#else
+ u16 par; /* 0x00 Pin Assignment */
+ u8 ddr; /* 0x02 Data Direction */
+ u8 ier; /* 0x03 Interrupt Enable */
+ u8 dr; /* 0x04 Data */
+ u8 pdr; /* 0x05 Pin Data */
+ u8 fr; /* 0x06 Flag */
+ u8 res0;
+#endif
+} eport_t;
+
+/* EPPAR */
+#define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2)
+#define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4)
+#define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6)
+#define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8)
+#define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10)
+#define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12)
+#define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14)
+#define EPORT_PAR_LEVEL (0)
+#define EPORT_PAR_RISING (1)
+#define EPORT_PAR_FALLING (2)
+#define EPORT_PAR_BOTH (3)
+#define EPORT_PAR_EPPA7_LEVEL (0x0000)
+#define EPORT_PAR_EPPA7_RISING (0x4000)
+#define EPORT_PAR_EPPA7_FALLING (0x8000)
+#define EPORT_PAR_EPPA7_BOTH (0xC000)
+#define EPORT_PAR_EPPA6_LEVEL (0x0000)
+#define EPORT_PAR_EPPA6_RISING (0x1000)
+#define EPORT_PAR_EPPA6_FALLING (0x2000)
+#define EPORT_PAR_EPPA6_BOTH (0x3000)
+#define EPORT_PAR_EPPA5_LEVEL (0x0000)
+#define EPORT_PAR_EPPA5_RISING (0x0400)
+#define EPORT_PAR_EPPA5_FALLING (0x0800)
+#define EPORT_PAR_EPPA5_BOTH (0x0C00)
+#define EPORT_PAR_EPPA4_LEVEL (0x0000)
+#define EPORT_PAR_EPPA4_RISING (0x0100)
+#define EPORT_PAR_EPPA4_FALLING (0x0200)
+#define EPORT_PAR_EPPA4_BOTH (0x0300)
+#define EPORT_PAR_EPPA3_LEVEL (0x0000)
+#define EPORT_PAR_EPPA3_RISING (0x0040)
+#define EPORT_PAR_EPPA3_FALLING (0x0080)
+#define EPORT_PAR_EPPA3_BOTH (0x00C0)
+#define EPORT_PAR_EPPA2_LEVEL (0x0000)
+#define EPORT_PAR_EPPA2_RISING (0x0010)
+#define EPORT_PAR_EPPA2_FALLING (0x0020)
+#define EPORT_PAR_EPPA2_BOTH (0x0030)
+#define EPORT_PAR_EPPA1_LEVEL (0x0000)
+#define EPORT_PAR_EPPA1_RISING (0x0004)
+#define EPORT_PAR_EPPA1_FALLING (0x0008)
+#define EPORT_PAR_EPPA1_BOTH (0x000C)
+
+/* EPDDR */
+#define EPORT_DDR_EPDD1 (0x02)
+#define EPORT_DDR_EPDD2 (0x04)
+#define EPORT_DDR_EPDD3 (0x08)
+#define EPORT_DDR_EPDD4 (0x10)
+#define EPORT_DDR_EPDD5 (0x20)
+#define EPORT_DDR_EPDD6 (0x40)
+#define EPORT_DDR_EPDD7 (0x80)
+
+/* EPIER */
+#define EPORT_IER_EPIE1 (0x02)
+#define EPORT_IER_EPIE2 (0x04)
+#define EPORT_IER_EPIE3 (0x08)
+#define EPORT_IER_EPIE4 (0x10)
+#define EPORT_IER_EPIE5 (0x20)
+#define EPORT_IER_EPIE6 (0x40)
+#define EPORT_IER_EPIE7 (0x80)
+
+/* EPDR */
+#define EPORT_DR_EPD1 (0x02)
+#define EPORT_DR_EPD2 (0x04)
+#define EPORT_DR_EPD3 (0x08)
+#define EPORT_DR_EPD4 (0x10)
+#define EPORT_DR_EPD5 (0x20)
+#define EPORT_DR_EPD6 (0x40)
+#define EPORT_DR_EPD7 (0x80)
+
+/* EPPDR */
+#define EPORT_PDR_EPPD1 (0x02)
+#define EPORT_PDR_EPPD2 (0x04)
+#define EPORT_PDR_EPPD3 (0x08)
+#define EPORT_PDR_EPPD4 (0x10)
+#define EPORT_PDR_EPPD5 (0x20)
+#define EPORT_PDR_EPPD6 (0x40)
+#define EPORT_PDR_EPPD7 (0x80)
+
+/* EPFR */
+#define EPORT_FR_EPF1 (0x02)
+#define EPORT_FR_EPF2 (0x04)
+#define EPORT_FR_EPF3 (0x08)
+#define EPORT_FR_EPF4 (0x10)
+#define EPORT_FR_EPF5 (0x20)
+#define EPORT_FR_EPF6 (0x40)
+#define EPORT_FR_EPF7 (0x80)
+
+#endif /* __EPORT_H__ */
diff --git a/arch/m68k/include/asm/coldfire/flexbus.h b/arch/m68k/include/asm/coldfire/flexbus.h
new file mode 100644
index 0000000..51cbbd8
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/flexbus.h
@@ -0,0 +1,120 @@
+/*
+ * FlexBus Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLEXBUS_H
+#define __FLEXBUS_H
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+
+typedef struct fbcs {
+ u32 csar0; /* Chip-select Address */
+ u32 csmr0; /* Chip-select Mask */
+ u32 cscr0; /* Chip-select Control */
+ u32 csar1;
+ u32 csmr1;
+ u32 cscr1;
+ u32 csar2;
+ u32 csmr2;
+ u32 cscr2;
+ u32 csar3;
+ u32 csmr3;
+ u32 cscr3;
+ u32 csar4;
+ u32 csmr4;
+ u32 cscr4;
+ u32 csar5;
+ u32 csmr5;
+ u32 cscr5;
+ u32 csar6;
+ u32 csmr6;
+ u32 cscr6;
+ u32 csar7;
+ u32 csmr7;
+ u32 cscr7;
+} fbcs_t;
+
+#define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000)
+
+#define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16)
+#define FBCS_CSMR_BAM_MASK (0x0000FFFF)
+#define FBCS_CSMR_BAM_4G (0xFFFF0000)
+#define FBCS_CSMR_BAM_2G (0x7FFF0000)
+#define FBCS_CSMR_BAM_1G (0x3FFF0000)
+#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
+#define FBCS_CSMR_BAM_512M (0x1FFF0000)
+#define FBCS_CSMR_BAM_256M (0x0FFF0000)
+#define FBCS_CSMR_BAM_128M (0x07FF0000)
+#define FBCS_CSMR_BAM_64M (0x03FF0000)
+#define FBCS_CSMR_BAM_32M (0x01FF0000)
+#define FBCS_CSMR_BAM_16M (0x00FF0000)
+#define FBCS_CSMR_BAM_8M (0x007F0000)
+#define FBCS_CSMR_BAM_4M (0x003F0000)
+#define FBCS_CSMR_BAM_2M (0x001F0000)
+#define FBCS_CSMR_BAM_1M (0x000F0000)
+#define FBCS_CSMR_BAM_1024K (0x000F0000)
+#define FBCS_CSMR_BAM_512K (0x00070000)
+#define FBCS_CSMR_BAM_256K (0x00030000)
+#define FBCS_CSMR_BAM_128K (0x00010000)
+#define FBCS_CSMR_BAM_64K (0x00000000)
+
+#ifdef CONFIG_M5249
+#define FBCS_CSMR_WP (0x00000080)
+#define FBCS_CSMR_AM (0x00000040)
+#define FBCS_CSMR_CI (0x00000020)
+#define FBCS_CSMR_SC (0x00000010)
+#define FBCS_CSMR_SD (0x00000008)
+#define FBCS_CSMR_UC (0x00000004)
+#define FBCS_CSMR_UD (0x00000002)
+#else
+#define FBCS_CSMR_WP (0x00000100)
+#endif
+#define FBCS_CSMR_V (0x00000001) /* Valid bit */
+
+#define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26)
+#define FBCS_CSCR_SWS_MASK (0x03FFFFFF)
+#define FBCS_CSCR_SWSEN (0x00800000)
+#define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20)
+#define FBCS_CSCR_ASET_MASK (0xFFCFFFFF)
+#define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18)
+#define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF)
+#define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16)
+#define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF)
+#define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10)
+#define FBCS_CSCR_WS_MASK (0xFFFF03FF)
+#define FBCS_CSCR_SBM (0x00000200)
+#define FBCS_CSCR_AA (0x00000100)
+#define FBCS_CSCR_PS(x) (((x) & 0x03) << 6)
+#define FBCS_CSCR_PS_MASK (0xFFFFFF3F)
+#define FBCS_CSCR_BEM (0x00000020)
+#define FBCS_CSCR_BSTR (0x00000010)
+#define FBCS_CSCR_BSTW (0x00000008)
+
+#define FBCS_CSCR_PS_16 (0x00000080)
+#define FBCS_CSCR_PS_8 (0x00000040)
+#define FBCS_CSCR_PS_32 (0x00000000)
+
+#endif /* __FLEXBUS_H */
diff --git a/arch/m68k/include/asm/coldfire/flexcan.h b/arch/m68k/include/asm/coldfire/flexcan.h
new file mode 100644
index 0000000..cafd44f
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/flexcan.h
@@ -0,0 +1,219 @@
+/*
+ * Flex CAN Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLEXCAN_H__
+#define __FLEXCAN_H__
+
+/* FlexCan Message Buffer */
+typedef struct can_msgbuf_ctrl {
+#ifdef CONFIG_M5282
+ u8 tmstamp; /* 0x00 Timestamp */
+ u8 ctrl; /* 0x01 Control */
+ u16 idh; /* 0x02 ID High */
+ u16 idl; /* 0x04 ID High */
+ u8 data[8]; /* 0x06 8 Byte Data Field */
+ u16 res; /* 0x0E */
+#else
+ u16 ctrl; /* 0x00 Control/Status */
+ u16 tmstamp; /* 0x02 Timestamp */
+ u32 id; /* 0x04 Identifier */
+ u8 data[8]; /* 0x08 8 Byte Data Field */
+#endif
+} can_msg_t;
+
+#ifdef CONFIG_M5282
+/* MSGBUF CTRL */
+#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x0F) << 4)
+#define CAN_MSGBUF_CTRL_CODE_MASK (0x0F)
+#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x0F)
+#define CAN_MSGBUF_CTRL_LEN_MASK (0xF0)
+
+/* MSGBUF ID */
+#define CAN_MSGBUF_IDH_STD(x) (((x) & 0x07FF) << 5)
+#define CAN_MSGBUF_IDH_STD_MASK (0xE003FFFF)
+#define CAN_MSGBUF_IDH_SRR (0x0010)
+#define CAN_MSGBUF_IDH_IDE (0x0080)
+#define CAN_MSGBUF_IDH_EXTH(x) ((x) & 0x07)
+#define CAN_MSGBUF_IDH_EXTH_MASK (0xFFF8)
+#define CAN_MSGBUF_IDL_EXTL(x) (((x) & 0x7FFF) << 1)
+#define CAN_MSGBUF_IDL_EXTL_MASK (0xFFFE)
+#define CAN_MSGBUF_IDL_RTR (0x0001)
+#else
+/* MSGBUF CTRL */
+#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x000F) << 8)
+#define CAN_MSGBUF_CTRL_CODE_MASK (0xF0FF)
+#define CAN_MSGBUF_CTRL_SRR (0x0040)
+#define CAN_MSGBUF_CTRL_IDE (0x0020)
+#define CAN_MSGBUF_CTRL_RTR (0x0010)
+#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x000F)
+#define CAN_MSGBUF_CTRL_LEN_MASK (0xFFF0)
+
+/* MSGBUF ID */
+#define CAN_MSGBUF_ID_STD(x) (((x) & 0x000007FF) << 18)
+#define CAN_MSGBUF_ID_STD_MASK (0xE003FFFF)
+#define CAN_MSGBUF_ID_EXT(x) ((x) & 0x0003FFFF)
+#define CAN_MSGBUF_ID_EXT_MASK (0xFFFC0000)
+#endif
+
+/* FlexCan module */
+typedef struct can_ctrl {
+ u32 mcr; /* 0x00 Module Configuration */
+ u32 ctrl; /* 0x04 Control */
+ u32 timer; /* 0x08 Free Running Timer */
+ u32 res1; /* 0x0C */
+ u32 rxgmsk; /* 0x10 Rx Global Mask */
+ u32 rx14msk; /* 0x14 RxBuffer 14 Mask */
+ u32 rx15msk; /* 0x18 RxBuffer 15 Mask */
+#ifdef CONFIG_M5282
+ u32 res2; /* 0x1C */
+ u16 errstat; /* 0x20 Error and status */
+ u16 imsk; /* 0x22 Interrupt Mask */
+ u16 iflag; /* 0x24 Interrupt Flag */
+ u16 errcnt; /* 0x26 Error Counter */
+ u32 res3[3]; /* 0x28 - 0x33 */
+#else
+ u16 res2; /* 0x1C */
+ u16 errcnt; /* 0x1E Error Counter */
+ u16 res3; /* 0x20 */
+ u16 errstat; /* 0x22 Error and status */
+ u32 res4; /* 0x24 */
+ u32 imsk; /* 0x28 Interrupt Mask */
+ u32 res5; /* 0x2C */
+ u16 iflag; /* 0x30 Interrupt Flag */
+#endif
+ u32 res6[19]; /* 0x34 - 0x7F */
+ void *msgbuf; /* 0x80 Message Buffer 0-15 */
+} can_t;
+
+/* MCR */
+#define CAN_MCR_MDIS (0x80000000)
+#define CAN_MCR_FRZ (0x40000000)
+#define CAN_MCR_HALT (0x10000000)
+#define CAN_MCR_NORDY (0x08000000)
+#define CAN_MCF_WAKEMSK (0x04000000) /* 5282 */
+#define CAN_MCR_SOFTRST (0x02000000)
+#define CAN_MCR_FRZACK (0x01000000)
+#define CAN_MCR_SUPV (0x00800000)
+#define CAN_MCR_SELFWAKE (0x00400000) /* 5282 */
+#define CAN_MCR_APS (0x00200000) /* 5282 */
+#define CAN_MCR_LPMACK (0x00100000)
+#define CAN_MCF_BCC (0x00010000)
+#define CAN_MCR_MAXMB(x) ((x) & 0x0F)
+#define CAN_MCR_MAXMB_MASK (0xFFFFFFF0)
+
+/* CTRL */
+#define CAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24)
+#define CAN_CTRL_PRESDIV_MASK (0x00FFFFFF)
+#define CAN_CTRL_RJW(x) (((x) & 0x03) << 22)
+#define CAN_CTRL_RJW_MASK (0xFF3FFFFF)
+#define CAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
+#define CAN_CTRL_PSEG1_MASK (0xFFC7FFFF)
+#define CAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
+#define CAN_CTRL_PSEG2_MASK (0xFFF8FFFF)
+#define CAN_CTRL_BOFFMSK (0x00008000)
+#define CAN_CTRL_ERRMSK (0x00004000)
+#define CAN_CTRL_CLKSRC (0x00002000)
+#define CAN_CTRL_LPB (0x00001000)
+#define CAN_CTRL_RXMODE (0x00000400) /* 5282 */
+#define CAN_CTRL_TXMODE(x) (((x) & 0x03) << 8) /* 5282 */
+#define CAN_CTRL_TXMODE_MASK (0xFFFFFCFF) /* 5282 */
+#define CAN_CTRL_TXMODE_CAN0 (0x00000000) /* 5282 */
+#define CAN_CTRL_TXMODE_CAN1 (0x00000100) /* 5282 */
+#define CAN_CTRL_TXMODE_OPEN (0x00000200) /* 5282 */
+#define CAN_CTRL_SMP (0x00000080)
+#define CAN_CTRL_BOFFREC (0x00000040)
+#define CAN_CTRL_TSYNC (0x00000020)
+#define CAN_CTRL_LBUF (0x00000010)
+#define CAN_CTRL_LOM (0x00000008)
+#define CAN_CTRL_PROPSEG(x) ((x) & 0x07)
+#define CAN_CTRL_PROPSEG_MASK (0xFFFFFFF8)
+
+/* TIMER */
+/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
+#define CAN_TIMER(x) ((x) & 0xFFFF)
+#define CAN_TIMER_MASK (0xFFFF0000)
+
+/* RXGMASK */
+#ifdef CONFIG_M5282
+#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 21)
+#define CAN_RXGMSK_MI_STD_MASK (0x001FFFFF)
+#define CAN_RXGMSK_MI_EXT(x) (((x) & 0x0003FFFF) << 1)
+#define CAN_RXGMSK_MI_EXT_MASK (0xFFF80001)
+#else
+#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 18)
+#define CAN_RXGMSK_MI_STD_MASK (0xE003FFFF)
+#define CAN_RXGMSK_MI_EXT(x) ((x) & 0x0003FFFF)
+#define CAN_RXGMSK_MI_EXT_MASK (0xFFFC0000)
+#endif
+
+/* ERRCNT */
+#define CAN_ERRCNT_RXECTR(x) (((x) & 0xFF) << 8)
+#define CAN_ERRCNT_RXECTR_MASK (0x00FF)
+#define CAN_ERRCNT_TXECTR(x) ((x) & 0xFF)
+#define CAN_ERRCNT_TXECTR_MASK (0xFF00)
+
+/* ERRSTAT */
+#define CAN_ERRSTAT_BITERR1 (0x8000)
+#define CAN_ERRSTAT_BITERR0 (0x4000)
+#define CAN_ERRSTAT_ACKERR (0x2000)
+#define CAN_ERRSTAT_CRCERR (0x1000)
+#define CAN_ERRSTAT_FRMERR (0x0800)
+#define CAN_ERRSTAT_STFERR (0x0400)
+#define CAN_ERRSTAT_TXWRN (0x0200)
+#define CAN_ERRSTAT_RXWRN (0x0100)
+#define CAN_ERRSTAT_IDLE (0x0080)
+#define CAN_ERRSTAT_TXRX (0x0040)
+#define CAN_ERRSTAT_FLT_MASK (0xFFCF)
+#define CAN_ERRSTAT_FLT_BUSOFF (0x0020)
+#define CAN_ERRSTAT_FLT_PASSIVE (0x0010)
+#define CAN_ERRSTAT_FLT_ACTIVE (0x0000)
+#ifdef CONFIG_M5282
+#define CAN_ERRSTAT_BOFFINT (0x0004)
+#define CAN_ERRSTAT_ERRINT (0x0002)
+#else
+#define CAN_ERRSTAT_ERRINT (0x0004)
+#define CAN_ERRSTAT_BOFFINT (0x0002)
+#define CAN_ERRSTAT_WAKEINT (0x0001)
+#endif
+
+/* IMASK */
+#ifdef CONFIG_M5253
+#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFFFFFF))
+#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
+#else
+#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFF))
+#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
+#endif
+
+/* IFLAG */
+#ifdef CONFIG_M5253
+#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFFFFFF))
+#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
+#else
+#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFF))
+#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
+#endif
+
+#endif /* __FLEXCAN_H__ */
diff --git a/arch/m68k/include/asm/coldfire/intctrl.h b/arch/m68k/include/asm/coldfire/intctrl.h
new file mode 100644
index 0000000..ae82b29
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/intctrl.h
@@ -0,0 +1,246 @@
+/*
+ * Interrupt Controller Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __INTCTRL_H__
+#define __INTCTRL_H__
+
+#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
+ defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
+ defined(CONFIG_M547x) || defined(CONFIG_M548x)
+# define CONFIG_SYS_CF_INTC_REG1
+#endif
+
+typedef struct int0_ctrl {
+ /* Interrupt Controller 0 */
+ u32 iprh0; /* 0x00 Pending High */
+ u32 iprl0; /* 0x04 Pending Low */
+ u32 imrh0; /* 0x08 Mask High */
+ u32 imrl0; /* 0x0C Mask Low */
+ u32 frch0; /* 0x10 Force High */
+ u32 frcl0; /* 0x14 Force Low */
+#if defined(CONFIG_SYS_CF_INTC_REG1)
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+#else
+ u16 res1; /* 0x18 - 0x19 */
+ u16 icfg0; /* 0x1A Configuration */
+ u8 simr0; /* 0x1C Set Interrupt Mask */
+ u8 cimr0; /* 0x1D Clear Interrupt Mask */
+ u8 clmask0; /* 0x1E Current Level Mask */
+ u8 slmask; /* 0x1F Saved Level Mask */
+ u32 res2[8]; /* 0x20 - 0x3F */
+#endif
+ u8 icr0[64]; /* 0x40 - 0x7F Control registers */
+ u32 res3[24]; /* 0x80 - 0xDF */
+ u8 swiack0; /* 0xE0 Software Interrupt ack */
+ u8 res4[3]; /* 0xE1 - 0xE3 */
+ u8 L1iack0; /* 0xE4 Level n interrupt ack */
+ u8 res5[3]; /* 0xE5 - 0xE7 */
+ u8 L2iack0; /* 0xE8 Level n interrupt ack */
+ u8 res6[3]; /* 0xE9 - 0xEB */
+ u8 L3iack0; /* 0xEC Level n interrupt ack */
+ u8 res7[3]; /* 0xED - 0xEF */
+ u8 L4iack0; /* 0xF0 Level n interrupt ack */
+ u8 res8[3]; /* 0xF1 - 0xF3 */
+ u8 L5iack0; /* 0xF4 Level n interrupt ack */
+ u8 res9[3]; /* 0xF5 - 0xF7 */
+ u8 L6iack0; /* 0xF8 Level n interrupt ack */
+ u8 resa[3]; /* 0xF9 - 0xFB */
+ u8 L7iack0; /* 0xFC Level n interrupt ack */
+ u8 resb[3]; /* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+ /* Interrupt Controller 1 */
+ u32 iprh1; /* 0x00 Pending High */
+ u32 iprl1; /* 0x04 Pending Low */
+ u32 imrh1; /* 0x08 Mask High */
+ u32 imrl1; /* 0x0C Mask Low */
+ u32 frch1; /* 0x10 Force High */
+ u32 frcl1; /* 0x14 Force Low */
+#if defined(CONFIG_SYS_CF_INTC_REG1)
+ u8 irlr; /* 0x18 */
+ u8 iacklpr; /* 0x19 */
+ u16 res1[19]; /* 0x1a - 0x3c */
+#else
+ u16 res1; /* 0x18 */
+ u16 icfg1; /* 0x1A Configuration */
+ u8 simr1; /* 0x1C Set Interrupt Mask */
+ u8 cimr1; /* 0x1D Clear Interrupt Mask */
+ u16 res2; /* 0x1E - 0x1F */
+ u32 res3[8]; /* 0x20 - 0x3F */
+#endif
+ u8 icr1[64]; /* 0x40 - 0x7F */
+ u32 res4[24]; /* 0x80 - 0xDF */
+ u8 swiack1; /* 0xE0 Software Interrupt ack */
+ u8 res5[3]; /* 0xE1 - 0xE3 */
+ u8 L1iack1; /* 0xE4 Level n interrupt ack */
+ u8 res6[3]; /* 0xE5 - 0xE7 */
+ u8 L2iack1; /* 0xE8 Level n interrupt ack */
+ u8 res7[3]; /* 0xE9 - 0xEB */
+ u8 L3iack1; /* 0xEC Level n interrupt ack */
+ u8 res8[3]; /* 0xED - 0xEF */
+ u8 L4iack1; /* 0xF0 Level n interrupt ack */
+ u8 res9[3]; /* 0xF1 - 0xF3 */
+ u8 L5iack1; /* 0xF4 Level n interrupt ack */
+ u8 resa[3]; /* 0xF5 - 0xF7 */
+ u8 L6iack1; /* 0xF8 Level n interrupt ack */
+ u8 resb[3]; /* 0xF9 - 0xFB */
+ u8 L7iack1; /* 0xFC Level n interrupt ack */
+ u8 resc[3]; /* 0xFD - 0xFF */
+} int1_t;
+
+typedef struct intgack_ctrl1 {
+ /* Global IACK Registers */
+ u8 swiack; /* 0x00 Global Software Interrupt ack */
+ u8 res0[0x3];
+ u8 gl1iack; /* 0x04 */
+ u8 resv1[0x3];
+ u8 gl2iack; /* 0x08 */
+ u8 res2[0x3];
+ u8 gl3iack; /* 0x0C */
+ u8 res3[0x3];
+ u8 gl4iack; /* 0x10 */
+ u8 res4[0x3];
+ u8 gl5iack; /* 0x14 */
+ u8 res5[0x3];
+ u8 gl6iack; /* 0x18 */
+ u8 res6[0x3];
+ u8 gl7iack; /* 0x1C */
+ u8 res7[0x3];
+} intgack_t;
+
+#define INTC_IPRH_INT63 (0x80000000)
+#define INTC_IPRH_INT62 (0x40000000)
+#define INTC_IPRH_INT61 (0x20000000)
+#define INTC_IPRH_INT60 (0x10000000)
+#define INTC_IPRH_INT59 (0x08000000)
+#define INTC_IPRH_INT58 (0x04000000)
+#define INTC_IPRH_INT57 (0x02000000)
+#define INTC_IPRH_INT56 (0x01000000)
+#define INTC_IPRH_INT55 (0x00800000)
+#define INTC_IPRH_INT54 (0x00400000)
+#define INTC_IPRH_INT53 (0x00200000)
+#define INTC_IPRH_INT52 (0x00100000)
+#define INTC_IPRH_INT51 (0x00080000)
+#define INTC_IPRH_INT50 (0x00040000)
+#define INTC_IPRH_INT49 (0x00020000)
+#define INTC_IPRH_INT48 (0x00010000)
+#define INTC_IPRH_INT47 (0x00008000)
+#define INTC_IPRH_INT46 (0x00004000)
+#define INTC_IPRH_INT45 (0x00002000)
+#define INTC_IPRH_INT44 (0x00001000)
+#define INTC_IPRH_INT43 (0x00000800)
+#define INTC_IPRH_INT42 (0x00000400)
+#define INTC_IPRH_INT41 (0x00000200)
+#define INTC_IPRH_INT40 (0x00000100)
+#define INTC_IPRH_INT39 (0x00000080)
+#define INTC_IPRH_INT38 (0x00000040)
+#define INTC_IPRH_INT37 (0x00000020)
+#define INTC_IPRH_INT36 (0x00000010)
+#define INTC_IPRH_INT35 (0x00000008)
+#define INTC_IPRH_INT34 (0x00000004)
+#define INTC_IPRH_INT33 (0x00000002)
+#define INTC_IPRH_INT32 (0x00000001)
+
+#define INTC_IPRL_INT31 (0x80000000)
+#define INTC_IPRL_INT30 (0x40000000)
+#define INTC_IPRL_INT29 (0x20000000)
+#define INTC_IPRL_INT28 (0x10000000)
+#define INTC_IPRL_INT27 (0x08000000)
+#define INTC_IPRL_INT26 (0x04000000)
+#define INTC_IPRL_INT25 (0x02000000)
+#define INTC_IPRL_INT24 (0x01000000)
+#define INTC_IPRL_INT23 (0x00800000)
+#define INTC_IPRL_INT22 (0x00400000)
+#define INTC_IPRL_INT21 (0x00200000)
+#define INTC_IPRL_INT20 (0x00100000)
+#define INTC_IPRL_INT19 (0x00080000)
+#define INTC_IPRL_INT18 (0x00040000)
+#define INTC_IPRL_INT17 (0x00020000)
+#define INTC_IPRL_INT16 (0x00010000)
+#define INTC_IPRL_INT15 (0x00008000)
+#define INTC_IPRL_INT14 (0x00004000)
+#define INTC_IPRL_INT13 (0x00002000)
+#define INTC_IPRL_INT12 (0x00001000)
+#define INTC_IPRL_INT11 (0x00000800)
+#define INTC_IPRL_INT10 (0x00000400)
+#define INTC_IPRL_INT9 (0x00000200)
+#define INTC_IPRL_INT8 (0x00000100)
+#define INTC_IPRL_INT7 (0x00000080)
+#define INTC_IPRL_INT6 (0x00000040)
+#define INTC_IPRL_INT5 (0x00000020)
+#define INTC_IPRL_INT4 (0x00000010)
+#define INTC_IPRL_INT3 (0x00000008)
+#define INTC_IPRL_INT2 (0x00000004)
+#define INTC_IPRL_INT1 (0x00000002)
+#define INTC_IPRL_INT0 (0x00000001)
+
+#define INTC_IMRLn_MASKALL (0x00000001)
+
+#define INTC_IRLR(x) (((x) & 0x7F) << 1)
+#define INTC_IRLR_MASK (0x01)
+
+#define INTC_IACKLPR_LVL(x) (((x) & 0x07) << 4)
+#define INTC_IACKLPR_LVL_MASK (0x8F)
+#define INTC_IACKLPR_PRI(x) ((x) & 0x0F)
+#define INTC_IACKLPR_PRI_MASK (0xF0)
+
+#if defined(CONFIG_SYS_CF_INTC_REG1)
+#define INTC_ICR_IL(x) (((x) & 0x07) << 3)
+#define INTC_ICR_IL_MASK (0xC7)
+#define INTC_ICR_IP(x) ((x) & 0x07)
+#define INTC_ICR_IP_MASK (0xF8)
+#else
+#define INTC_ICR_IL(x) ((x) & 0x07)
+#define INTC_ICR_IL_MASK (0xF8)
+#endif
+
+#define INTC_ICONFIG_ELVLPRI_MASK (0x01FF)
+#define INTC_ICONFIG_ELVLPRI7 (0x8000)
+#define INTC_ICONFIG_ELVLPRI6 (0x4000)
+#define INTC_ICONFIG_ELVLPRI5 (0x2000)
+#define INTC_ICONFIG_ELVLPRI4 (0x1000)
+#define INTC_ICONFIG_ELVLPRI3 (0x0800)
+#define INTC_ICONFIG_ELVLPRI2 (0x0400)
+#define INTC_ICONFIG_ELVLPRI1 (0x0200)
+#define INTC_ICONFIG_EMASK (0x0020)
+
+#define INTC_SIMR_ALL (0x40)
+#define INTC_SIMR(x) ((x) & 0x3F)
+#define INTC_SIMR_MASK (0x80)
+
+#define INTC_CIMR_ALL (0x40)
+#define INTC_CIMR(x) ((x) & 0x3F)
+#define INTC_CIMR_MASK (0x80)
+
+#define INTC_CLMASK(x) ((x) & 0x0F)
+#define INTC_CLMASK_MASK (0xF0)
+
+#define INTC_SLMASK(x) ((x) & 0x0F)
+#define INTC_SLMASK_MASK (0xF0)
+
+#endif /* __INTCTRL_H__ */
diff --git a/arch/m68k/include/asm/coldfire/lcd.h b/arch/m68k/include/asm/coldfire/lcd.h
new file mode 100644
index 0000000..66b95b3
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/lcd.h
@@ -0,0 +1,213 @@
+/*
+ * LCD controller Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LCDC_H__
+#define __LCDC_H__
+
+/* LCD module registers */
+typedef struct lcd_ctrl {
+ u32 ssar; /* 0x00 Screen Start Address Register */
+ u32 sr; /* 0x04 LCD Size Register */
+ u32 vpw; /* 0x08 Virtual Page Width Register */
+ u32 cpr; /* 0x0C Cursor Position Register */
+ u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
+ u32 ccmr; /* 0x14 Color Cursor Mapping Register */
+ u32 pcr; /* 0x18 Panel Configuration Register */
+ u32 hcr; /* 0x1C Horizontal Configuration Register */
+ u32 vcr; /* 0x20 Vertical Configuration Register */
+ u32 por; /* 0x24 Panning Offset Register */
+ u32 scr; /* 0x28 Sharp Configuration Register */
+ u32 pccr; /* 0x2C PWM Contrast Control Register */
+ u32 dcr; /* 0x30 DMA Control Register */
+ u32 rmcr; /* 0x34 Refresh Mode Control Register */
+ u32 icr; /* 0x38 Refresh Mode Control Register */
+ u32 ier; /* 0x3C Interrupt Enable Register */
+ u32 isr; /* 0x40 Interrupt Status Register */
+ u32 res[4];
+ u32 gwsar; /* 0x50 Graphic Window Start Address Register */
+ u32 gwsr; /* 0x54 Graphic Window Size Register */
+ u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
+ u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
+ u32 gwpr; /* 0x60 Graphic Window Position Register */
+ u32 gwcr; /* 0x64 Graphic Window Control Register */
+ u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
+} lcd_t;
+
+typedef struct lcdbg_ctrl {
+ u32 bglut[255];
+} lcdbg_t;
+
+typedef struct lcdgw_ctrl {
+ u32 gwlut[255];
+} lcdgw_t;
+
+/* Bit definitions and macros for LCDC_LSSAR */
+#define LCDC_SSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LSR */
+#define LCDC_SR_XMAX(x) (((x)&0x0000003F)<<20)
+#define LCDC_SR_YMAX(x) ((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LVPWR */
+#define LCDC_VPWR_VPW(x) (((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LCPR */
+#define LCDC_CPR_CC(x) (((x)&0x00000003)<<30)
+#define LCDC_CPR_CC_AND (0xC0000000)
+#define LCDC_CPR_CC_XOR (0x80000000)
+#define LCDC_CPR_CC_OR (0x40000000)
+#define LCDC_CPR_CC_TRANSPARENT (0x00000000)
+#define LCDC_CPR_OP (0x10000000)
+#define LCDC_CPR_CXP(x) (((x)&0x000003FF)<<16)
+#define LCDC_CPR_CYP(x) ((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LCWHBR */
+#define LCDC_CWHBR_BK_EN (0x80000000)
+#define LCDC_CWHBR_CW(x) (((x)&0x0000001F)<<24)
+#define LCDC_CWHBR_CH(x) (((x)&0x0000001F)<<16)
+#define LCDC_CWHBR_BD(x) ((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_LCCMR */
+#define LCDC_CCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
+#define LCDC_CCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
+#define LCDC_CCMR_CUR_COL_B(x) ((x)&0x0000003F)
+
+/* Bit definitions and macros for LCDC_LPCR */
+#define LCDC_PCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
+#define LCDC_PCR_MODE_TFT (0xC0000000)
+#define LCDC_PCR_MODE_CSTN (0x40000000)
+#define LCDC_PCR_MODE_MONOCHROME (0x00000000)
+#define LCDC_PCR_TFT (0x80000000)
+#define LCDC_PCR_COLOR (0x40000000)
+#define LCDC_PCR_PBSIZ(x) (((x)&0x00000003)<<28)
+#define LCDC_PCR_PBSIZ_8 (0x30000000)
+#define LCDC_PCR_PBSIZ_4 (0x20000000)
+#define LCDC_PCR_PBSIZ_2 (0x10000000)
+#define LCDC_PCR_PBSIZ_1 (0x00000000)
+#define LCDC_PCR_BPIX(x) (((x)&0x00000007)<<25)
+#define LCDC_PCR_BPIX_18bpp (0x0C000000)
+#define LCDC_PCR_BPIX_16bpp (0x0A000000)
+#define LCDC_PCR_BPIX_12bpp (0x08000000)
+#define LCDC_PCR_BPIX_8bpp (0x06000000)
+#define LCDC_PCR_BPIX_4bpp (0x04000000)
+#define LCDC_PCR_BPIX_2bpp (0x02000000)
+#define LCDC_PCR_BPIX_1bpp (0x00000000)
+#define LCDC_PCR_PIXPOL (0x01000000)
+#define LCDC_PCR_FLM (0x00800000)
+#define LCDC_PCR_LPPOL (0x00400000)
+#define LCDC_PCR_CLKPOL (0x00200000)
+#define LCDC_PCR_OEPOL (0x00100000)
+#define LCDC_PCR_SCLKIDLE (0x00080000)
+#define LCDC_PCR_ENDSEL (0x00040000)
+#define LCDC_PCR_SWAP_SEL (0x00020000)
+#define LCDC_PCR_REV_VS (0x00010000)
+#define LCDC_PCR_ACDSEL (0x00008000)
+#define LCDC_PCR_ACD(x) (((x)&0x0000007F)<<8)
+#define LCDC_PCR_SCLKSEL (0x00000080)
+#define LCDC_PCR_SHARP (0x00000040)
+#define LCDC_PCR_PCD(x) ((x)&0x0000003F)
+
+/* Bit definitions and macros for LCDC_LHCR */
+#define LCDC_HCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
+#define LCDC_HCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
+#define LCDC_HCR_H_WAIT_2(x) ((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_LVCR */
+#define LCDC_VCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
+#define LCDC_VCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
+#define LCDC_VCR_V_WAIT_2(x) ((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_SCR */
+#define LCDC_SCR_PS_R_DELAY(x) (((x)&0x0000003F) << 26)
+#define LCDC_SCR_CLS_R_DELAY(x) (((x)&0x000000FF) << 16)
+#define LCDC_SCR_RTG_DELAY(x) (((x)&0x0000000F) << 8)
+#define LCDC_SCR_GRAY2(x) (((x)&0x0000000F) << 4)
+#define LCDC_SCR_GRAY1(x) ((x)&&0x0000000F)
+
+/* Bit definitions and macros for LCDC_LPCCR */
+#define LCDC_PCCR_CLS_HI_WID(x) (((x)&0x000001FF)<<16)
+#define LCDC_PCCR_LDMSK (0x00008000)
+#define LCDC_PCCR_SCR(x) (((x)&0x00000003)<<9)
+#define LCDC_PCCR_SCR_LCDCLK (0x00000400)
+#define LCDC_PCCR_SCR_PIXCLK (0x00000200)
+#define LCDC_PCCR_SCR_LNPULSE (0x00000000)
+#define LCDC_PCCR_CC_EN (0x00000100)
+#define LCDC_PCCR_PW(x) ((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_LDCR */
+#define LCDC_DCR_BURST (0x80000000)
+#define LCDC_DCR_HM(x) (((x)&0x0000001F)<<16)
+#define LCDC_DCR_TM(x) ((x)&0x0000001F)
+
+/* Bit definitions and macros for LCDC_LRMCR */
+#define LCDC_RMCR_SEL_REF (0x00000001)
+
+/* Bit definitions and macros for LCDC_LICR */
+#define LCDC_ICR_GW_INT_CON (0x00000010)
+#define LCDC_ICR_INTSYN (0x00000004)
+#define LCDC_ICR_INTCON (0x00000001)
+
+/* Bit definitions and macros for LCDC_LIER */
+#define LCDC_IER_GW_UDR (0x00000080)
+#define LCDC_IER_GW_ERR (0x00000040)
+#define LCDC_IER_GW_EOF (0x00000020)
+#define LCDC_IER_GW_BOF (0x00000010)
+#define LCDC_IER_UDR (0x00000008)
+#define LCDC_IER_ERR (0x00000004)
+#define LCDC_IER_EOF (0x00000002)
+#define LCDC_IER_BOF (0x00000001)
+
+/* Bit definitions and macros for LCDC_LGWSAR */
+#define LCDC_GWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LGWSR */
+#define LCDC_GWSR_GWW(x) (((x)&0x0000003F)<<20)
+#define LCDC_GWSR_GWH(x) ((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LGWVPWR */
+#define LCDC_GWVPWR_GWVPW(x) ((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LGWPOR */
+#define LCDC_GWPOR_GWPO(x) ((x)&0x0000001F)
+
+/* Bit definitions and macros for LCDC_LGWPR */
+#define LCDC_GWPR_GWXP(x) (((x)&0x000003FF)<<16)
+#define LCDC_GWPR_GWYP(x) ((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LGWCR */
+#define LCDC_GWCR_GWAV(x) (((x)&0x000000FF)<<24)
+#define LCDC_GWCR_GWCKE (0x00800000)
+#define LCDC_LGWCR_GWE (0x00400000)
+#define LCDC_LGWCR_GW_RVS (0x00200000)
+#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
+#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
+#define LCDC_LGWCR_GWCKB(x) ((x)&0x0000003F)
+
+/* Bit definitions and macros for LCDC_LGWDCR */
+#define LCDC_LGWDCR_GWBT (0x80000000)
+#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
+#define LCDC_LGWDCR_GWTM(x) ((x)&0x0000001F)
+
+#endif /* __LCDC_H__ */
diff --git a/arch/m68k/include/asm/coldfire/mdha.h b/arch/m68k/include/asm/coldfire/mdha.h
new file mode 100644
index 0000000..b6981363
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/mdha.h
@@ -0,0 +1,102 @@
+/*
+ * Message Digest Hardware Accelerator Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MDHA_H__
+#define __MDHA_H__
+
+/* Message Digest Hardware Accelerator */
+typedef struct mdha_ctrl {
+ u32 mr; /* 0x00 MDHA Mode */
+ u32 cr; /* 0x04 Control */
+ u32 cmd; /* 0x08 Command */
+ u32 sr; /* 0x0C Status */
+ u32 isr; /* 0x10 Interrupt Status */
+ u32 imr; /* 0x14 Interrupt Mask */
+ u32 dsz; /* 0x1C Data Size */
+ u32 inp; /* 0x20 Input FIFO */
+ u32 res1[3]; /* 0x24 - 0x2F */
+ u32 mda0; /* 0x30 Message Digest AO */
+ u32 mdb0; /* 0x34 Message Digest BO */
+ u32 mdc0; /* 0x38 Message Digest CO */
+ u32 mdd0; /* 0x3C Message Digest DO */
+ u32 mde0; /* 0x40 Message Digest EO */
+ u32 mdsz; /* 0x44 Message Data Size */
+ u32 res[10]; /* 0x48 - 0x6F */
+ u32 mda1; /* 0x70 Message Digest A1 */
+ u32 mdb1; /* 0x74 Message Digest B1 */
+ u32 mdc1; /* 0x78 Message Digest C1 */
+ u32 mdd1; /* 0x7C Message Digest D1 */
+ u32 mde1; /* 0x80 Message Digest E1 */
+} mdha_t;
+
+#define MDHA_MR_SSL (0x00000400)
+#define MDHA_MR_MACFUL (0x00000200)
+#define MDHA_MR_SWAP (0x00000100)
+#define MDHA_MR_OPAD (0x00000080)
+#define MDHA_MR_IPAD (0x00000040)
+#define MDHA_MR_INIT (0x00000020)
+#define MDHA_MR_MAC(x) (((x) & 0x03) << 3)
+#define MDHA_MR_MAC_MASK (0xFFFFFFE7)
+#define MDHA_MR_MAC_EHMAC (0x00000010)
+#define MDHA_MR_MAC_HMAC (0x00000008)
+#define MDHA_MR_MAC_NONE (0x00000000)
+#define MDHA_MR_PDATA (0x00000004)
+#define MDHA_MR_ALG (0x00000001)
+
+#define MDHA_CR_DMAL(x) (((x) & 0x1F) << 16) /* 532x */
+#define MDHA_CR_DMAL_MASK (0xFFE0FFFF) /* 532x */
+#define MDHA_CR_END (0x00000004) /* 532x */
+#define MDHA_CR_DMA (0x00000002) /* 532x */
+#define MDHA_CR_IE (0x00000001)
+
+#define MDHA_CMD_GO (0x00000008)
+#define MDHA_CMD_CI (0x00000004)
+#define MDHA_CMD_RI (0x00000001)
+#define MDHA_CMD_SWR (0x00000001)
+
+#define MDHA_SR_IFL(x) (((x) & 0xFF) << 16)
+#define MDHA_SR_IFL_MASK (0xFF00FFFF)
+#define MDHA_SR_APD(x) (((x) & 0x7) << 13)
+#define MDHA_SR_APD_MASK (0xFFFF1FFF)
+#define MDHA_SR_FS(x) (((x) & 0x7) << 8)
+#define MDHA_SR_FS_MASK (0xFFFFF8FF)
+#define MDHA_SR_GNW (0x00000080)
+#define MDHA_SR_HSH (0x00000040)
+#define MDHA_SR_BUSY (0x00000010)
+#define MDHA_SR_RD (0x00000008)
+#define MDHA_SR_ERR (0x00000004)
+#define MDHA_SR_DONE (0x00000002)
+#define MDHA_SR_INT (0x00000001)
+
+#define MDHA_ISR_DRL (0x00000400) /* 532x */
+#define MDHA_ISR_GTDS (0x00000200)
+#define MDHA_ISR_ERE (0x00000100)
+#define MDHA_ISR_RMDP (0x00000080)
+#define MDHA_ISR_DSE (0x00000020)
+#define MDHA_ISR_IME (0x00000010)
+#define MDHA_ISR_NEIF (0x00000004)
+#define MDHA_ISR_IFO (0x00000001)
+
+#endif /* __MDHA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/pwm.h b/arch/m68k/include/asm/coldfire/pwm.h
new file mode 100644
index 0000000..f737d98
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/pwm.h
@@ -0,0 +1,115 @@
+/*
+ * Pulse Width Modulation Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ATA_H__
+#define __ATA_H__
+
+/* Pulse Width Modulation (PWM) */
+typedef struct pwm_ctrl {
+#ifdef CONFIG_M5272
+ u8 cr0;
+ u8 res1[3];
+ u8 cr1;
+ u8 res2[3];
+ u8 cr2;
+ u8 res3[7];
+ u8 pwr0;
+ u8 res4[3];
+ u8 pwr1;
+ u8 res5[3];
+ u8 pwr2;
+ u8 res6[7];
+#else
+ u8 en; /* 0x00 PWM Enable */
+ u8 pol; /* 0x01 Polarity */
+ u8 clk; /* 0x02 Clock Select */
+ u8 prclk; /* 0x03 Prescale Clock Select */
+ u8 cae; /* 0x04 Center Align Enable */
+ u8 ctl; /* 0x05 Control */
+ u16 res1; /* 0x06 - 0x07 */
+ u8 scla; /* 0x08 Scale A */
+ u8 sclb; /* 0x09 Scale B */
+ u16 res2; /* 0x0A - 0x0B */
+#ifdef CONFIG_M5275
+ u8 cnt[4]; /* 0x0C Channel n Counter */
+ u16 res3; /* 0x10 - 0x11 */
+ u8 per[4]; /* 0x14 Channel n Period */
+ u16 res4; /* 0x16 - 0x17 */
+ u8 dty[4]; /* 0x18 Channel n Duty */
+#else
+ u8 cnt[8]; /* 0x0C Channel n Counter */
+ u8 per[8]; /* 0x14 Channel n Period */
+ u8 dty[8]; /* 0x1C Channel n Duty */
+ u8 sdn; /* 0x24 Shutdown */
+ u8 res3[3]; /* 0x25 - 0x27 */
+#endif /* CONFIG_M5275 */
+#endif /* CONFIG_M5272 */
+} pwm_t;
+
+#ifdef CONFIG_M5272
+
+#define PWM_CR_EN (0x80)
+#define PWM_CR_FRC1 (0x40)
+#define PWM_CR_LVL (0x20)
+#define PWM_CR_CLKSEL(x) ((x) & 0x0F)
+#define PWM_CR_CLKSEL_MASK (0xF0)
+
+#else
+
+#define PWM_EN_PWMEn(x) (1 << ((x) & 0x07))
+#define PWM_EN_PWMEn_MASK (0xF0)
+
+#define PWM_POL_PPOLn(x) (1 << ((x) & 0x07))
+#define PWM_POL_PPOLn_MASK (0xF0)
+
+#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
+#define PWM_CLK_PCLKn_MASK (0xF0)
+
+#define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4)
+#define PWM_PRCLK_PCKB_MASK (0x8F)
+#define PWM_PRCLK_PCKA(x) ((x) & 0x07)
+#define PWM_PRCLK_PCKA_MASK (0xF8)
+
+#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
+#define PWM_CLK_PCLKn_MASK (0xF0)
+
+#define PWM_CTL_CON67 (0x80)
+#define PWM_CTL_CON45 (0x40)
+#define PWM_CTL_CON23 (0x20)
+#define PWM_CTL_CON01 (0x10)
+#define PWM_CTL_PSWAR (0x08)
+#define PWM_CTL_PFRZ (0x04)
+
+#define PWM_SDN_IF (0x80)
+#define PWM_SDN_IE (0x40)
+#define PWM_SDN_RESTART (0x20)
+#define PWM_SDN_LVL (0x10)
+#define PWM_SDN_PWM7IN (0x04)
+#define PWM_SDN_PWM7IL (0x02)
+#define PWM_SDN_SDNEN (0x01)
+
+#endif /* CONFIG_M5272 */
+
+#endif /* __ATA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/qspi.h b/arch/m68k/include/asm/coldfire/qspi.h
new file mode 100644
index 0000000..8bcd2e4
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/qspi.h
@@ -0,0 +1,111 @@
+/*
+ * Queue Serial Peripheral Interface Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __QSPI_H__
+#define __QSPI_H__
+
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+ u16 mr; /* 0x00 Mode */
+ u16 res1;
+ u16 dlyr; /* 0x04 Delay */
+ u16 res2;
+ u16 wr; /* 0x08 Wrap */
+ u16 res3;
+ u16 ir; /* 0x0C Interrupt */
+ u16 res4;
+ u16 ar; /* 0x10 Address */
+ u16 res5;
+ u16 dr; /* 0x14 Data */
+ u16 res6;
+} qspi_t;
+
+/* MR */
+#define QSPI_QMR_MSTR (0x8000)
+#define QSPI_QMR_DOHIE (0x4000)
+#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
+#define QSPI_QMR_BITS_MASK (0xC3FF)
+#define QSPI_QMR_BITS_8 (0x2000)
+#define QSPI_QMR_BITS_9 (0x2400)
+#define QSPI_QMR_BITS_10 (0x2800)
+#define QSPI_QMR_BITS_11 (0x2C00)
+#define QSPI_QMR_BITS_12 (0x3000)
+#define QSPI_QMR_BITS_13 (0x3400)
+#define QSPI_QMR_BITS_14 (0x3800)
+#define QSPI_QMR_BITS_15 (0x3C00)
+#define QSPI_QMR_BITS_16 (0x0000)
+#define QSPI_QMR_CPOL (0x0200)
+#define QSPI_QMR_CPHA (0x0100)
+#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
+#define QSPI_QMR_BAUD_MASK (0xFF00)
+
+/* DLYR */
+#define QSPI_QDLYR_SPE (0x8000)
+#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
+#define QSPI_QDLYR_QCD_MASK (0x80FF)
+#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
+#define QSPI_QDLYR_DTL_MASK (0xFF00)
+
+/* WR */
+#define QSPI_QWR_HALT (0x8000)
+#define QSPI_QWR_WREN (0x4000)
+#define QSPI_QWR_WRTO (0x2000)
+#define QSPI_QWR_CSIV (0x1000)
+#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
+#define QSPI_QWR_ENDQP_MASK (0xF0FF)
+#define QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
+#define QSPI_QWR_CPTQP_MASK (0xFF0F)
+#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
+#define QSPI_QWR_NEWQP_MASK (0xFFF0)
+
+/* IR */
+#define QSPI_QIR_WCEFB (0x8000)
+#define QSPI_QIR_ABRTB (0x4000)
+#define QSPI_QIR_ABRTL (0x1000)
+#define QSPI_QIR_WCEFE (0x0800)
+#define QSPI_QIR_ABRTE (0x0400)
+#define QSPI_QIR_SPIFE (0x0100)
+#define QSPI_QIR_WCEF (0x0008)
+#define QSPI_QIR_ABRT (0x0004)
+#define QSPI_QIR_SPIF (0x0001)
+
+/* AR */
+#define QSPI_QAR_ADDR(x) ((x)&0x003F)
+#define QSPI_QAR_ADDR_MASK (0xFFC0)
+#define QSPI_QAR_TRANS (0x0000)
+#define QSPI_QAR_RECV (0x0010)
+#define QSPI_QAR_CMD (0x0020)
+
+/* DR */
+#define QSPI_QDR_CONT (0x8000)
+#define QSPI_QDR_BITSE (0x4000)
+#define QSPI_QDR_DT (0x2000)
+#define QSPI_QDR_DSCK (0x1000)
+#define QSPI_QDR_QSPI_CS3 (0x0800)
+#define QSPI_QDR_QSPI_CS2 (0x0400)
+#define QSPI_QDR_QSPI_CS1 (0x0200)
+#define QSPI_QDR_QSPI_CS0 (0x0100)
+
+#endif /* __QSPI_H__ */
diff --git a/arch/m68k/include/asm/coldfire/rng.h b/arch/m68k/include/asm/coldfire/rng.h
new file mode 100644
index 0000000..1eefc56
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/rng.h
@@ -0,0 +1,52 @@
+/*
+ * RNG Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __RNG_H__
+#define __RNG_H__
+
+/* Random Number Generator */
+typedef struct rng_ctrl {
+ u32 cr; /* 0x00 Control */
+ u32 sr; /* 0x04 Status */
+ u32 er; /* 0x08 Entropy */
+ u32 out; /* 0x0C Output FIFO */
+} rng_t;
+
+#define RNG_CR_SLM (0x00000010) /* Sleep mode - 5445x */
+#define RNG_CR_CI (0x00000008) /* Clear interrupt */
+#define RNG_CR_IM (0x00000004) /* Interrupt mask */
+#define RNG_CR_HA (0x00000002) /* High assurance */
+#define RNG_CR_GO (0x00000001) /* Go bit */
+
+#define RNG_SR_OFS(x) (((x) & 0x000000FF) << 16)
+#define RNG_SR_OFS_MASK (0xFF00FFFF)
+#define RNG_SR_OFL(x) (((x) & 0x000000FF) << 8)
+#define RNG_SR_OFL_MASK (0xFFFF00FF)
+#define RNG_SR_EI (0x00000008)
+#define RNG_SR_FUF (0x00000004)
+#define RNG_SR_LRS (0x00000002)
+#define RNG_SR_SV (0x00000001)
+
+#endif /* __RNG_H__ */
diff --git a/arch/m68k/include/asm/coldfire/skha.h b/arch/m68k/include/asm/coldfire/skha.h
new file mode 100644
index 0000000..bd6b5af
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/skha.h
@@ -0,0 +1,121 @@
+/*
+ * Symmetric Key Hardware Accelerator Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SKHA_H__
+#define __SKHA_H__
+
+typedef struct skha_ctrl {
+ u32 mr; /* 0x00 Mode */
+ u32 cr; /* 0x04 Control */
+ u32 cmr; /* 0x08 Command */
+ u32 sr; /* 0x0C Status */
+ u32 esr; /* 0x10 Error Status */
+ u32 emr; /* 0x14 Error Status Mask Register) */
+ u32 ksr; /* 0x18 Key Size */
+ u32 dsr; /* 0x1C Data Size */
+ u32 in; /* 0x20 Input FIFO */
+ u32 out; /* 0x24 Output FIFO */
+ u32 res1[2]; /* 0x28 - 0x2F */
+ u32 kdr1; /* 0x30 Key Data 1 */
+ u32 kdr2; /* 0x34 Key Data 2 */
+ u32 kdr3; /* 0x38 Key Data 3 */
+ u32 kdr4; /* 0x3C Key Data 4 */
+ u32 kdr5; /* 0x40 Key Data 5 */
+ u32 kdr6; /* 0x44 Key Data 6 */
+ u32 res2[10]; /* 0x48 - 0x6F */
+ u32 c1; /* 0x70 Context 1 */
+ u32 c2; /* 0x74 Context 2 */
+ u32 c3; /* 0x78 Context 3 */
+ u32 c4; /* 0x7C Context 4 */
+ u32 c5; /* 0x80 Context 5 */
+ u32 c6; /* 0x84 Context 6 */
+ u32 c7; /* 0x88 Context 7 */
+ u32 c8; /* 0x8C Context 8 */
+ u32 c9; /* 0x90 Context 9 */
+ u32 c10; /* 0x94 Context 10 */
+ u32 c11; /* 0x98 Context 11 */
+ u32 c12; /* 0x9C Context 12 - 5235, 5271, 5272 */
+} skha_t;
+
+#ifdef CONFIG_MCF532x
+#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 9)
+#define SKHA_MODE_CTRM_MASK (0xFFFFE1FF)
+#define SKHA_MODE_DKP (0x00000100)
+#else
+#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 8)
+#define SKHA_MODE_CTRM_MASK (0xFFFFF0FF)
+#define SKHA_MODE_DKP (0x00000080)
+#endif
+#define SKHA_MODE_CM(x) (((x) & 0x03) << 3)
+#define SKHA_MODE_CM_MASK (0xFFFFFFE7)
+#define SKHA_MODE_DIR (0x00000004)
+#define SKHA_MODE_ALG(x) ((x) & 0x03)
+#define SKHA_MODE_ALG_MASK (0xFFFFFFFC)
+
+#define SHKA_CR_ODMAL(x) (((x) & 0x3F) << 24)
+#define SHKA_CR_ODMAL_MASK (0xC0FFFFFF)
+#define SHKA_CR_IDMAL(x) (((x) & 0x3F) << 16)
+#define SHKA_CR_IDMAL_MASK (0xFFC0FFFF)
+#define SHKA_CR_END (0x00000008)
+#define SHKA_CR_ODMA (0x00000004)
+#define SHKA_CR_IDMA (0x00000002)
+#define SKHA_CR_IE (0x00000001)
+
+#define SKHA_CMR_GO (0x00000008)
+#define SKHA_CMR_CI (0x00000004)
+#define SKHA_CMR_RI (0x00000002)
+#define SKHA_CMR_SWR (0x00000001)
+
+#define SKHA_SR_OFL(x) (((x) & 0xFF) << 24)
+#define SKHA_SR_OFL_MASK (0x00FFFFFF)
+#define SKHA_SR_IFL(x) (((x) & 0xFF) << 16)
+#define SKHA_SR_IFL_MASK (0xFF00FFFF)
+#define SKHA_SR_AESES(x) (((x) & 0x1F) << 11)
+#define SKHA_SR_AESES_MASK (0xFFFF07FF)
+#define SKHA_SR_DESES(x) (((x) & 0x7) << 8)
+#define SKHA_SR_DESES_MASK (0xFFFFF8FF)
+#define SKHA_SR_BUSY (0x00000010)
+#define SKHA_SR_RD (0x00000008)
+#define SKHA_SR_ERR (0x00000004)
+#define SKHA_SR_DONE (0x00000002)
+#define SKHA_SR_INT (0x00000001)
+
+#define SHKA_ESE_DRL (0x00000800)
+#define SKHA_ESR_KRE (0x00000400)
+#define SKHA_ESR_KPE (0x00000200)
+#define SKHA_ESR_ERE (0x00000100)
+#define SKHA_ESR_RMDP (0x00000080)
+#define SKHA_ESR_KSE (0x00000040)
+#define SKHA_ESR_DSE (0x00000020)
+#define SKHA_ESR_IME (0x00000010)
+#define SKHA_ESR_NEOF (0x00000008)
+#define SKHA_ESR_NEIF (0x00000004)
+#define SKHA_ESR_OFU (0x00000002)
+#define SKHA_ESR_IFO (0x00000001)
+
+#define SKHA_KSR_SZ(x) ((x) & 0x3F)
+#define SKHA_KSR_SZ_MASK (0xFFFFFFC0)
+
+#endif /* __SKHA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/ssi.h b/arch/m68k/include/asm/coldfire/ssi.h
new file mode 100644
index 0000000..b3dfbfa
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/ssi.h
@@ -0,0 +1,169 @@
+/*
+ * SSI Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SSI_H__
+#define __SSI_H__
+
+typedef struct ssi {
+ u32 tx0;
+ u32 tx1;
+ u32 rx0;
+ u32 rx1;
+ u32 cr;
+ u32 isr;
+ u32 ier;
+ u32 tcr;
+ u32 rcr;
+ u32 ccr;
+ u8 resv0[0x4];
+ u32 fcsr;
+ u8 resv1[0x8];
+ u32 acr;
+ u32 acadd;
+ u32 acdat;
+ u32 atag;
+ u32 tmask;
+ u32 rmask;
+} ssi_t;
+
+#define SSI_CR_CIS (0x00000200)
+#define SSI_CR_TCH (0x00000100)
+#define SSI_CR_MCE (0x00000080)
+#define SSI_CR_I2S_MASK (0xFFFFFF9F)
+#define SSI_CR_I2S_SLAVE (0x00000040)
+#define SSI_CR_I2S_MASTER (0x00000020)
+#define SSI_CR_I2S_NORMAL (0x00000000)
+#define SSI_CR_SYN (0x00000010)
+#define SSI_CR_NET (0x00000008)
+#define SSI_CR_RE (0x00000004)
+#define SSI_CR_TE (0x00000002)
+#define SSI_CR_SSI_EN (0x00000001)
+
+#define SSI_ISR_CMDAU (0x00040000)
+#define SSI_ISR_CMDDU (0x00020000)
+#define SSI_ISR_RXT (0x00010000)
+#define SSI_ISR_RDR1 (0x00008000)
+#define SSI_ISR_RDR0 (0x00004000)
+#define SSI_ISR_TDE1 (0x00002000)
+#define SSI_ISR_TDE0 (0x00001000)
+#define SSI_ISR_ROE1 (0x00000800)
+#define SSI_ISR_ROE0 (0x00000400)
+#define SSI_ISR_TUE1 (0x00000200)
+#define SSI_ISR_TUE0 (0x00000100)
+#define SSI_ISR_TFS (0x00000080)
+#define SSI_ISR_RFS (0x00000040)
+#define SSI_ISR_TLS (0x00000020)
+#define SSI_ISR_RLS (0x00000010)
+#define SSI_ISR_RFF1 (0x00000008)
+#define SSI_ISR_RFF0 (0x00000004)
+#define SSI_ISR_TFE1 (0x00000002)
+#define SSI_ISR_TFE0 (0x00000001)
+
+#define SSI_IER_RDMAE (0x00400000)
+#define SSI_IER_RIE (0x00200000)
+#define SSI_IER_TDMAE (0x00100000)
+#define SSI_IER_TIE (0x00080000)
+#define SSI_IER_CMDAU (0x00040000)
+#define SSI_IER_CMDU (0x00020000)
+#define SSI_IER_RXT (0x00010000)
+#define SSI_IER_RDR1 (0x00008000)
+#define SSI_IER_RDR0 (0x00004000)
+#define SSI_IER_TDE1 (0x00002000)
+#define SSI_IER_TDE0 (0x00001000)
+#define SSI_IER_ROE1 (0x00000800)
+#define SSI_IER_ROE0 (0x00000400)
+#define SSI_IER_TUE1 (0x00000200)
+#define SSI_IER_TUE0 (0x00000100)
+#define SSI_IER_TFS (0x00000080)
+#define SSI_IER_RFS (0x00000040)
+#define SSI_IER_TLS (0x00000020)
+#define SSI_IER_RLS (0x00000010)
+#define SSI_IER_RFF1 (0x00000008)
+#define SSI_IER_RFF0 (0x00000004)
+#define SSI_IER_TFE1 (0x00000002)
+#define SSI_IER_TFE0 (0x00000001)
+
+#define SSI_TCR_TXBIT0 (0x00000200)
+#define SSI_TCR_TFEN1 (0x00000100)
+#define SSI_TCR_TFEN0 (0x00000080)
+#define SSI_TCR_TFDIR (0x00000040)
+#define SSI_TCR_TXDIR (0x00000020)
+#define SSI_TCR_TSHFD (0x00000010)
+#define SSI_TCR_TSCKP (0x00000008)
+#define SSI_TCR_TFSI (0x00000004)
+#define SSI_TCR_TFSL (0x00000002)
+#define SSI_TCR_TEFS (0x00000001)
+
+#define SSI_RCR_RXEXT (0x00000400)
+#define SSI_RCR_RXBIT0 (0x00000200)
+#define SSI_RCR_RFEN1 (0x00000100)
+#define SSI_RCR_RFEN0 (0x00000080)
+#define SSI_RCR_RSHFD (0x00000010)
+#define SSI_RCR_RSCKP (0x00000008)
+#define SSI_RCR_RFSI (0x00000004)
+#define SSI_RCR_RFSL (0x00000002)
+#define SSI_RCR_REFS (0x00000001)
+
+#define SSI_CCR_DIV2 (0x00040000)
+#define SSI_CCR_PSR (0x00020000)
+#define SSI_CCR_WL(x) (((x) & 0x0F) << 13)
+#define SSI_CCR_WL_MASK (0xFFFE1FFF)
+#define SSI_CCR_DC(x) (((x)& 0x1F) << 8)
+#define SSI_CCR_DC_MASK (0xFFFFE0FF)
+#define SSI_CCR_PM(x) ((x) & 0xFF)
+#define SSI_CCR_PM_MASK (0xFFFFFF00)
+
+#define SSI_FCSR_RFCNT1(x) (((x) & 0x0F) << 28)
+#define SSI_FCSR_RFCNT1_MASK (0x0FFFFFFF)
+#define SSI_FCSR_TFCNT1(x) (((x) & 0x0F) << 24)
+#define SSI_FCSR_TFCNT1_MASK (0xF0FFFFFF)
+#define SSI_FCSR_RFWM1(x) (((x) & 0x0F) << 20)
+#define SSI_FCSR_RFWM1_MASK (0xFF0FFFFF)
+#define SSI_FCSR_TFWM1(x) (((x) & 0x0F) << 16)
+#define SSI_FCSR_TFWM1_MASK (0xFFF0FFFF)
+#define SSI_FCSR_RFCNT0(x) (((x) & 0x0F) << 12)
+#define SSI_FCSR_RFCNT0_MASK (0xFFFF0FFF)
+#define SSI_FCSR_TFCNT0(x) (((x) & 0x0F) << 8)
+#define SSI_FCSR_TFCNT0_MASK (0xFFFFF0FF)
+#define SSI_FCSR_RFWM0(x) (((x) & 0x0F) << 4)
+#define SSI_FCSR_RFWM0_MASK (0xFFFFFF0F)
+#define SSI_FCSR_TFWM0(x) ((x) & 0x0F)
+#define SSI_FCSR_TFWM0_MASK (0xFFFFFFF0)
+
+#define SSI_ACR_FRDIV(x) (((x) & 0x3F) << 5)
+#define SSI_ACR_FRDIV_MASK (0xFFFFF81F)
+#define SSI_ACR_WR (0x00000010)
+#define SSI_ACR_RD (0x00000008)
+#define SSI_ACR_TIF (0x00000004)
+#define SSI_ACR_FV (0x00000002)
+#define SSI_ACR_AC97EN (0x00000001)
+
+#define SSI_ACADD_SSI_ACADD(x) ((x) & 0x0007FFFF)
+
+#define SSI_ACDAT_SSI_ACDAT(x) ((x) & 0x0007FFFF)
+
+#define SSI_ATAG_DDI_ATAG(x) ((x) & 0x0000FFFF)
+
+#endif /* __SSI_H__ */