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authorRichard Retanubun <RichardRetanubun@RuggedCom.com>2011-03-24 08:58:11 +0000
committerjason <jason@jason-ThinkPad-T61.(none)>2012-09-20 20:39:27 +0800
commit59d0612252a0ffcb878a1891249d32a306a24fa6 (patch)
treeeef4fe1f59521cf6a2096434f0c600b1e82fc138 /arch/m68k/cpu/mcf52x2
parent198cafbf2cab9851ee5dd8d24d268d0ccc0fe3bd (diff)
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ColdFire: Queued SPI driver
This patch adds a driver for Freescale Colfire Queued SPI bus. Coded to work with 8 bits per transfer to use with SPI flash. CPOL, CPHA, and CS_ACTIVE_HIGH can be configured. Tested with MCF5270 which have 4 chip selects. Activate by #define CONFIG_CF_QSPI in board config. Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
Diffstat (limited to 'arch/m68k/cpu/mcf52x2')
-rw-r--r--arch/m68k/cpu/mcf52x2/cpu_init.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index a221420..5d0e9f0 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c
@@ -333,7 +333,20 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
return 0;
}
#endif /* CONFIG_CMD_NET */
-#endif
+
+#if defined(CONFIG_CF_QSPI)
+
+/* Configure PIOs for SIN, SOUT, and SCK */
+void cfspi_port_conf(void)
+{
+ mbar_writeByte(MCF_GPIO_PAR_QSPI,
+ MCF_GPIO_PAR_QSPI_SIN_SIN |
+ MCF_GPIO_PAR_QSPI_SOUT_SOUT |
+ MCF_GPIO_PAR_QSPI_SCK_SCK);
+}
+#endif /* CONFIG_CF_QSPI */
+
+#endif /* CONFIG_M5271 */
#if defined(CONFIG_M5272)
/*