ColdFire: Clean up checkpatch warnings for MCF52x2

Signed-off-by: Alison Wang <b18965@freescale.com>

1 files changed, 129 insertions, 123 deletions

diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index a98a926..a221420 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c
@@ -8,7 +8,7 @@
  * (c) Copyright 2010
  * Arcturus Networks Inc. <www.arcturusnetworks.com>
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
@@ -37,6 +37,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
@@ -48,57 +49,57 @@
 /* Only 5272 Flexbus chipselect is different from the rest */
 void init_fbcs(void)
 {
-	volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+	fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #else
 #warning "Chip Select 0 are not initialized/used"
 #endif
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
      && defined(CONFIG_SYS_CS6_CTRL))
-	fbcs->csar6 = CONFIG_SYS_CS6_BASE;
-	fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
-	fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
      && defined(CONFIG_SYS_CS7_CTRL))
-	fbcs->csar7 = CONFIG_SYS_CS7_BASE;
-	fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
-	fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
 #endif
 }
 #endif
@@ -106,22 +107,22 @@ void init_fbcs(void)
 #if defined(CONFIG_M5208)
 void cpu_init_f(void)
 {
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 
 #ifndef CONFIG_WATCHDOG
-	volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+	wdog_t *wdg = (wdog_t *) MMAP_WDOG;
 
 	/* Disable the watchdog if we aren't using it */
-	wdg->cr = 0;
+	out_be16(&wdg->cr, 0);
 #endif
 
-	scm1->mpr = 0x77777777;
-	scm1->pacra = 0;
-	scm1->pacrb = 0;
-	scm1->pacrc = 0;
-	scm1->pacrd = 0;
-	scm1->pacre = 0;
-	scm1->pacrf = 0;
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
 
 	/* FlexBus Chipselect */
 	init_fbcs();
@@ -137,36 +138,36 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 		break;
 	case 1:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-		gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+		clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+		setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
 		break;
 	case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
-		gpio->par_timer &=
-		    (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
-		gpio->par_timer |=
-		    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+		clrbits_8(&gpio->par_timer,
+			~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
+		setbits_8(&gpio->par_timer,
+			GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+		clrbits_8(&gpio->par_feci2c,
+			~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+		clrbits_8(&gpio->par_feci2c,
+			~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 #endif
 		break;
 	}
@@ -175,17 +176,17 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	if (setclear) {
-		gpio->par_fec |=
-		    GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
-		gpio->par_feci2c |=
-		    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+		setbits_8(&gpio->par_fec,
+			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+		setbits_8(&gpio->par_feci2c,
+			GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
 	} else {
-		gpio->par_fec &=
-		    (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
-		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
+		clrbits_8(&gpio->par_fec,
+			~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
+		clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
 	}
 	return 0;
 }
@@ -249,17 +250,17 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile u32 *par = (u32 *) MMAP_PAR;
+	u32 *par = (u32 *) MMAP_PAR;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 1:
-		*par &= 0xFFE7FFFF;
-		*par |= 0x00180000;
+		clrbits_be32(par, 0x00180000);
+		setbits_be32(par, 0x00180000);
 		break;
 	case 2:
-		*par &= 0xFFFFFFFC;
-		*par &= 0x00000003;
+		clrbits_be32(par, 0x00000003);
+		clrbits_be32(par, 0xFFFFFFFC);
 		break;
 	}
 }
@@ -348,59 +349,59 @@ void cpu_init_f(void)
 	 * already initialized.
 	 */
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
-	volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
-	volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
+	sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+	gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+	csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
 
-	sysctrl->sc_scr = CONFIG_SYS_SCR;
-	sysctrl->sc_spr = CONFIG_SYS_SPR;
+	out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
+	out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
 
 	/* Setup Ports: */
-	gpio->gpio_pacnt = CONFIG_SYS_PACNT;
-	gpio->gpio_paddr = CONFIG_SYS_PADDR;
-	gpio->gpio_padat = CONFIG_SYS_PADAT;
-	gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
-	gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
-	gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
-	gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
+	out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
+	out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
+	out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
+	out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
+	out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
+	out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
+	out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
 
 	/* Memory Controller: */
-	csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
-	csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
+	out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
+	out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
 
 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
-	csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
-	csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
+	out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
+	out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-	csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
-	csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
+	out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
+	out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
-	csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
-	csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
+	out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
+	out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
-	csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
-	csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
+	out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
+	out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
-	csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
-	csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
+	out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
+	out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
-	csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
-	csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
+	out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
+	out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
-	csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
-	csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
+	out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
+	out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
 #endif
 
 #endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
@@ -420,17 +421,21 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
-		gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+		clrbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+		setbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
 		break;
 	case 1:
-		gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
-		gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+		clrbits_be32(&gpio->gpio_pdcnt,
+			GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+		setbits_be32(&gpio->gpio_pdcnt,
+			GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
 		break;
 	}
 }
@@ -438,13 +443,14 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	if (setclear) {
-		gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
-				    GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
-				    GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
-				    GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+		setbits_be32(&gpio->gpio_pbcnt,
+			GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+			GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+			GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+			GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
 	} else {
 	}
 	return 0;
@@ -469,11 +475,11 @@ void cpu_init_f(void)
 	 */
 
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
-	volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
+	wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+	gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
 
 	/* Kill watchdog so we can initialize the PLL */
-	wdog_reg->wcr = 0;
+	out_be16(&wdog_reg->wcr, 0);
 
 	/* FlexBus Chipselect */
 	init_fbcs();
@@ -498,21 +504,21 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
 	switch (port) {
 	case 0:
-		gpio->par_uart &= ~UART0_ENABLE_MASK;
-		gpio->par_uart |= UART0_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
 		break;
 	case 1:
-		gpio->par_uart &= ~UART1_ENABLE_MASK;
-		gpio->par_uart |= UART1_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
 		break;
 	case 2:
-		gpio->par_uart &= ~UART2_ENABLE_MASK;
-		gpio->par_uart |= UART2_ENABLE_MASK;
+		clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
+		setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
 		break;
 	}
 }
@@ -521,24 +527,24 @@ void uart_port_conf(int port)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
 	struct fec_info_s *info = (struct fec_info_s *) dev->priv;
-	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 
 	if (setclear) {
 		/* Enable Ethernet pins */
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c |= 0x0F00;
-			gpio->par_fec0hl |= 0xC0;
+			setbits_be16(&gpio->par_feci2c, 0x0f00);
+			setbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
-			gpio->par_feci2c |= 0x00A0;
-			gpio->par_fec1hl |= 0xC0;
+			setbits_be16(&gpio->par_feci2c, 0x00a0);
+			setbits_8(&gpio->par_fec1hl, 0xc0);
 		}
 	} else {
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c &= ~0x0F00;
-			gpio->par_fec0hl &= ~0xC0;
+			clrbits_be16(&gpio->par_feci2c, 0x0f00);
+			clrbits_8(&gpio->par_fec0hl, 0xc0);
 		} else {
-			gpio->par_feci2c &= ~0x00A0;
-			gpio->par_fec1hl &= ~0xC0;
+			clrbits_be16(&gpio->par_feci2c, 0x00a0);
+			clrbits_8(&gpio->par_fec1hl, 0xc0);
 		}
 	}