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| author | Mike Frysinger <vapier@gentoo.org> | 2010-10-14 14:22:02 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-10-14 20:23:26 -0400 |
| commit | e5d8984be69f74627623573dc9bcf60711bfdfbf (patch) | |
| tree | 0b88bbe5db0eb39f867f78ecaf2a4ccb3c0351c2 /arch/blackfin/include/asm/mach-bf561 | |
| parent | e79f48393dd919079b34f37957c933f8e75c164d (diff) | |
| download | u-boot-imx-e5d8984be69f74627623573dc9bcf60711bfdfbf.zip u-boot-imx-e5d8984be69f74627623573dc9bcf60711bfdfbf.tar.gz u-boot-imx-e5d8984be69f74627623573dc9bcf60711bfdfbf.tar.bz2 | |
Blackfin: update anomaly lists to latest sheets
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include/asm/mach-bf561')
| -rw-r--r-- | arch/blackfin/include/asm/mach-bf561/anomaly.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h index 4c108c9..9313c27 100644 --- a/arch/blackfin/include/asm/mach-bf561/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf561/anomaly.h @@ -11,7 +11,7 @@ */ /* This file should be up to date with: - * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List + * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -286,12 +286,18 @@ #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* SCKELOW Feature Is Not Functional */ +#define ANOMALY_05000458 (1) /* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ +#define ANOMALY_05000471 (1) /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ #define ANOMALY_05000473 (1) /* Possible Lockup Condition whem Modifying PLL from External Memory */ -#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) +#define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ @@ -316,6 +322,7 @@ #define ANOMALY_05000430 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) +#define ANOMALY_05000440 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) #define ANOMALY_05000456 (0) |