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authorDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>2011-07-27 13:22:38 +0200
committerShinya Kuribayashi <skuribay@pobox.com>2011-07-31 23:26:41 +0900
commitab2a98b11716364bc5a8c43cdfa7fee176cda1d8 (patch)
treef6d237d468eec036180a987fa99a8f58aa907e89 /arch/blackfin/include/asm/mach-bf548
parent7185adb48ef1e5b0f05263a7f791de340ddddeb2 (diff)
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MIPS: make cache operation mode configurable
Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
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