diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2010-07-26 01:06:37 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-10-02 16:00:38 -0400 |
| commit | c489762ac21e3bb2cd562eb6b9f91d97dfce4b70 (patch) | |
| tree | ca892daeb5ea5e728dcacbccec81ab339617c3ed /arch/blackfin/include/asm/mach-bf533 | |
| parent | 9615398dc2829e06b4ea538836361310f58b3aaa (diff) | |
| download | u-boot-imx-c489762ac21e3bb2cd562eb6b9f91d97dfce4b70.zip u-boot-imx-c489762ac21e3bb2cd562eb6b9f91d97dfce4b70.tar.gz u-boot-imx-c489762ac21e3bb2cd562eb6b9f91d97dfce4b70.tar.bz2 | |
Blackfin: bf533: merge headers
Only the BF533 port was using the common extended headers, so merge them
into the BF533 specific headers.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include/asm/mach-bf533')
| -rw-r--r-- | arch/blackfin/include/asm/mach-bf533/BF531_cdef.h | 862 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mach-bf533/BF531_def.h | 428 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mach-bf533/BF532_cdef.h | 15 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mach-bf533/BF532_def.h | 6 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mach-bf533/BF533_cdef.h | 15 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mach-bf533/BF533_def.h | 4 |
6 files changed, 1293 insertions, 37 deletions
diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h index 49a2b2e..2572bfa 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h +++ b/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h @@ -8,7 +8,865 @@ #include "../mach-common/ADSP-EDN-core_cdef.h" -#include "../mach-common/ADSP-EDN-extended_cdef.h" - +#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D) +#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val) +#define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D) +#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val) +#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D) +#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val) +#define bfin_read_MDMAFLX0_YCOUNT_D() bfin_read16(MDMAFLX0_YCOUNT_D) +#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val) +#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D) +#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val) +#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D) +#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val) +#define bfin_read_MDMAFLX0_PMAP_D() bfin_read16(MDMAFLX0_PMAP_D) +#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val) +#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D) +#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val) +#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D) +#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val) +#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S) +#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val) +#define bfin_read_MDMAFLX0_XCOUNT_S() bfin_read16(MDMAFLX0_XCOUNT_S) +#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val) +#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S) +#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val) +#define bfin_read_MDMAFLX0_YCOUNT_S() bfin_read16(MDMAFLX0_YCOUNT_S) +#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val) +#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S) +#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val) +#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S) +#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val) +#define bfin_read_MDMAFLX0_PMAP_S() bfin_read16(MDMAFLX0_PMAP_S) +#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val) +#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S) +#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val) +#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S) +#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val) +#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D) +#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val) +#define bfin_read_MDMAFLX1_XCOUNT_D() bfin_read16(MDMAFLX1_XCOUNT_D) +#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val) +#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D) +#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val) +#define bfin_read_MDMAFLX1_YCOUNT_D() bfin_read16(MDMAFLX1_YCOUNT_D) +#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val) +#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D) +#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val) +#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D) +#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val) +#define bfin_read_MDMAFLX1_PMAP_D() bfin_read16(MDMAFLX1_PMAP_D) +#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val) +#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D) +#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val) +#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D) +#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val) +#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S) +#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val) +#define bfin_read_MDMAFLX1_XCOUNT_S() bfin_read16(MDMAFLX1_XCOUNT_S) +#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val) +#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S) +#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val) +#define bfin_read_MDMAFLX1_YCOUNT_S() bfin_read16(MDMAFLX1_YCOUNT_S) +#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val) +#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S) +#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val) +#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S) +#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val) +#define bfin_read_MDMAFLX1_PMAP_S() bfin_read16(MDMAFLX1_PMAP_S) +#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val) +#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S) +#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val) +#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S) +#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val) +#define bfin_read_DMAFLX0_DMACNFG() bfin_read16(DMAFLX0_DMACNFG) +#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val) +#define bfin_read_DMAFLX0_XCOUNT() bfin_read16(DMAFLX0_XCOUNT) +#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val) +#define bfin_read_DMAFLX0_XMODIFY() bfin_read16(DMAFLX0_XMODIFY) +#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val) +#define bfin_read_DMAFLX0_YCOUNT() bfin_read16(DMAFLX0_YCOUNT) +#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val) +#define bfin_read_DMAFLX0_YMODIFY() bfin_read16(DMAFLX0_YMODIFY) +#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val) +#define bfin_read_DMAFLX0_IRQSTAT() bfin_read16(DMAFLX0_IRQSTAT) +#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val) +#define bfin_read_DMAFLX0_PMAP() bfin_read16(DMAFLX0_PMAP) +#define bfin_write_DMAFLX0_PMAP(val) bfin_write16(DMAFLX0_PMAP, val) +#define bfin_read_DMAFLX0_CURXCOUNT() bfin_read16(DMAFLX0_CURXCOUNT) +#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val) +#define bfin_read_DMAFLX0_CURYCOUNT() bfin_read16(DMAFLX0_CURYCOUNT) +#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val) +#define bfin_read_DMAFLX1_DMACNFG() bfin_read16(DMAFLX1_DMACNFG) +#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val) +#define bfin_read_DMAFLX1_XCOUNT() bfin_read16(DMAFLX1_XCOUNT) +#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val) +#define bfin_read_DMAFLX1_XMODIFY() bfin_read16(DMAFLX1_XMODIFY) +#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val) +#define bfin_read_DMAFLX1_YCOUNT() bfin_read16(DMAFLX1_YCOUNT) +#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val) +#define bfin_read_DMAFLX1_YMODIFY() bfin_read16(DMAFLX1_YMODIFY) +#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val) +#define bfin_read_DMAFLX1_IRQSTAT() bfin_read16(DMAFLX1_IRQSTAT) +#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val) +#define bfin_read_DMAFLX1_PMAP() bfin_read16(DMAFLX1_PMAP) +#define bfin_write_DMAFLX1_PMAP(val) bfin_write16(DMAFLX1_PMAP, val) +#define bfin_read_DMAFLX1_CURXCOUNT() bfin_read16(DMAFLX1_CURXCOUNT) +#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val) +#define bfin_read_DMAFLX1_CURYCOUNT() bfin_read16(DMAFLX1_CURYCOUNT) +#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val) +#define bfin_read_DMAFLX2_DMACNFG() bfin_read16(DMAFLX2_DMACNFG) +#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val) +#define bfin_read_DMAFLX2_XCOUNT() bfin_read16(DMAFLX2_XCOUNT) +#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val) +#define bfin_read_DMAFLX2_XMODIFY() bfin_read16(DMAFLX2_XMODIFY) +#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val) +#define bfin_read_DMAFLX2_YCOUNT() bfin_read16(DMAFLX2_YCOUNT) +#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val) +#define bfin_read_DMAFLX2_YMODIFY() bfin_read16(DMAFLX2_YMODIFY) +#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val) +#define bfin_read_DMAFLX2_IRQSTAT() bfin_read16(DMAFLX2_IRQSTAT) +#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val) +#define bfin_read_DMAFLX2_PMAP() bfin_read16(DMAFLX2_PMAP) +#define bfin_write_DMAFLX2_PMAP(val) bfin_write16(DMAFLX2_PMAP, val) +#define bfin_read_DMAFLX2_CURXCOUNT() bfin_read16(DMAFLX2_CURXCOUNT) +#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val) +#define bfin_read_DMAFLX2_CURYCOUNT() bfin_read16(DMAFLX2_CURYCOUNT) +#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val) +#define bfin_read_DMAFLX3_DMACNFG() bfin_read16(DMAFLX3_DMACNFG) +#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val) +#define bfin_read_DMAFLX3_XCOUNT() bfin_read16(DMAFLX3_XCOUNT) +#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val) +#define bfin_read_DMAFLX3_XMODIFY() bfin_read16(DMAFLX3_XMODIFY) +#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val) +#define bfin_read_DMAFLX3_YCOUNT() bfin_read16(DMAFLX3_YCOUNT) +#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val) +#define bfin_read_DMAFLX3_YMODIFY() bfin_read16(DMAFLX3_YMODIFY) +#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val) +#define bfin_read_DMAFLX3_IRQSTAT() bfin_read16(DMAFLX3_IRQSTAT) +#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val) +#define bfin_read_DMAFLX3_PMAP() bfin_read16(DMAFLX3_PMAP) +#define bfin_write_DMAFLX3_PMAP(val) bfin_write16(DMAFLX3_PMAP, val) +#define bfin_read_DMAFLX3_CURXCOUNT() bfin_read16(DMAFLX3_CURXCOUNT) +#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val) +#define bfin_read_DMAFLX3_CURYCOUNT() bfin_read16(DMAFLX3_CURYCOUNT) +#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val) +#define bfin_read_DMAFLX4_DMACNFG() bfin_read16(DMAFLX4_DMACNFG) +#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val) +#define bfin_read_DMAFLX4_XCOUNT() bfin_read16(DMAFLX4_XCOUNT) +#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val) +#define bfin_read_DMAFLX4_XMODIFY() bfin_read16(DMAFLX4_XMODIFY) +#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val) +#define bfin_read_DMAFLX4_YCOUNT() bfin_read16(DMAFLX4_YCOUNT) +#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val) +#define bfin_read_DMAFLX4_YMODIFY() bfin_read16(DMAFLX4_YMODIFY) +#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val) +#define bfin_read_DMAFLX4_IRQSTAT() bfin_read16(DMAFLX4_IRQSTAT) +#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val) +#define bfin_read_DMAFLX4_PMAP() bfin_read16(DMAFLX4_PMAP) +#define bfin_write_DMAFLX4_PMAP(val) bfin_write16(DMAFLX4_PMAP, val) +#define bfin_read_DMAFLX4_CURXCOUNT() bfin_read16(DMAFLX4_CURXCOUNT) +#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val) +#define bfin_read_DMAFLX4_CURYCOUNT() bfin_read16(DMAFLX4_CURYCOUNT) +#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val) +#define bfin_read_DMAFLX5_DMACNFG() bfin_read16(DMAFLX5_DMACNFG) +#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val) +#define bfin_read_DMAFLX5_XCOUNT() bfin_read16(DMAFLX5_XCOUNT) +#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val) +#define bfin_read_DMAFLX5_XMODIFY() bfin_read16(DMAFLX5_XMODIFY) +#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val) +#define bfin_read_DMAFLX5_YCOUNT() bfin_read16(DMAFLX5_YCOUNT) +#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val) +#define bfin_read_DMAFLX5_YMODIFY() bfin_read16(DMAFLX5_YMODIFY) +#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val) +#define bfin_read_DMAFLX5_IRQSTAT() bfin_read16(DMAFLX5_IRQSTAT) +#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val) +#define bfin_read_DMAFLX5_PMAP() bfin_read16(DMAFLX5_PMAP) +#define bfin_write_DMAFLX5_PMAP(val) bfin_write16(DMAFLX5_PMAP, val) +#define bfin_read_DMAFLX5_CURXCOUNT() bfin_read16(DMAFLX5_CURXCOUNT) +#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val) +#define bfin_read_DMAFLX5_CURYCOUNT() bfin_read16(DMAFLX5_CURYCOUNT) +#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val) +#define bfin_read_DMAFLX6_DMACNFG() bfin_read16(DMAFLX6_DMACNFG) +#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val) +#define bfin_read_DMAFLX6_XCOUNT() bfin_read16(DMAFLX6_XCOUNT) +#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val) +#define bfin_read_DMAFLX6_XMODIFY() bfin_read16(DMAFLX6_XMODIFY) +#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val) +#define bfin_read_DMAFLX6_YCOUNT() bfin_read16(DMAFLX6_YCOUNT) +#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val) +#define bfin_read_DMAFLX6_YMODIFY() bfin_read16(DMAFLX6_YMODIFY) +#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val) +#define bfin_read_DMAFLX6_IRQSTAT() bfin_read16(DMAFLX6_IRQSTAT) +#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val) +#define bfin_read_DMAFLX6_PMAP() bfin_read16(DMAFLX6_PMAP) +#define bfin_write_DMAFLX6_PMAP(val) bfin_write16(DMAFLX6_PMAP, val) +#define bfin_read_DMAFLX6_CURXCOUNT() bfin_read16(DMAFLX6_CURXCOUNT) +#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val) +#define bfin_read_DMAFLX6_CURYCOUNT() bfin_read16(DMAFLX6_CURYCOUNT) +#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val) +#define bfin_read_DMAFLX7_DMACNFG() bfin_read16(DMAFLX7_DMACNFG) +#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val) +#define bfin_read_DMAFLX7_XCOUNT() bfin_read16(DMAFLX7_XCOUNT) +#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val) +#define bfin_read_DMAFLX7_XMODIFY() bfin_read16(DMAFLX7_XMODIFY) +#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val) +#define bfin_read_DMAFLX7_YCOUNT() bfin_read16(DMAFLX7_YCOUNT) +#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val) +#define bfin_read_DMAFLX7_YMODIFY() bfin_read16(DMAFLX7_YMODIFY) +#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val) +#define bfin_read_DMAFLX7_IRQSTAT() bfin_read16(DMAFLX7_IRQSTAT) +#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val) +#define bfin_read_DMAFLX7_PMAP() bfin_read16(DMAFLX7_PMAP) +#define bfin_write_DMAFLX7_PMAP(val) bfin_write16(DMAFLX7_PMAP, val) +#define bfin_read_DMAFLX7_CURXCOUNT() bfin_read16(DMAFLX7_CURXCOUNT) +#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val) +#define bfin_read_DMAFLX7_CURYCOUNT() bfin_read16(DMAFLX7_CURYCOUNT) +#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val) +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) +#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) +#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) +#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) +#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) +#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val) +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) +#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) +#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) +#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) +#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) +#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) +#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) +#define bfin_read_UART_THR() bfin_read16(UART_THR) +#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val) +#define bfin_read_UART_DLL() bfin_read16(UART_DLL) +#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val) +#define bfin_read_UART_DLH() bfin_read16(UART_DLH) +#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val) +#define bfin_read_UART_IER() bfin_read16(UART_IER) +#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val) +#define bfin_read_UART_IIR() bfin_read16(UART_IIR) +#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val) +#define bfin_read_UART_LCR() bfin_read16(UART_LCR) +#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val) +#define bfin_read_UART_MCR() bfin_read16(UART_MCR) +#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val) +#define bfin_read_UART_LSR() bfin_read16(UART_LSR) +#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val) +#define bfin_read_UART_SCR() bfin_read16(UART_SCR) +#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val) +#define bfin_read_UART_RBR() bfin_read16(UART_RBR) +#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val) +#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) +#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val) +#define bfin_read_SPT0_TX_CONFIG0() bfin_read16(SPT0_TX_CONFIG0) +#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val) +#define bfin_read_SPT0_TX_CONFIG1() bfin_read16(SPT0_TX_CONFIG1) +#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val) +#define bfin_read_SPT0_RX_CONFIG0() bfin_read16(SPT0_RX_CONFIG0) +#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val) +#define bfin_read_SPT0_RX_CONFIG1() bfin_read16(SPT0_RX_CONFIG1) +#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val) +#define bfin_read_SPT0_TX() bfin_read32(SPT0_TX) +#define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val) +#define bfin_read_SPT0_RX() bfin_read32(SPT0_RX) +#define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val) +#define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV) +#define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val) +#define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV) +#define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val) +#define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV) +#define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val) +#define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV) +#define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val) +#define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT) +#define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val) +#define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0) +#define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val) +#define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1) +#define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val) +#define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2) +#define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val) +#define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3) +#define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val) +#define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0) +#define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val) +#define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1) +#define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val) +#define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2) +#define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val) +#define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3) +#define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val) +#define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1) +#define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val) +#define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2) +#define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val) +#define bfin_read_SPT0_CHNL() bfin_read16(SPT0_CHNL) +#define bfin_write_SPT0_CHNL(val) bfin_write16(SPT0_CHNL, val) +#define bfin_read_SPT1_TX_CONFIG0() bfin_read16(SPT1_TX_CONFIG0) +#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val) +#define bfin_read_SPT1_TX_CONFIG1() bfin_read16(SPT1_TX_CONFIG1) +#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val) +#define bfin_read_SPT1_RX_CONFIG0() bfin_read16(SPT1_RX_CONFIG0) +#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val) +#define bfin_read_SPT1_RX_CONFIG1() bfin_read16(SPT1_RX_CONFIG1) +#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val) +#define bfin_read_SPT1_TX() bfin_read16(SPT1_TX) +#define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val) +#define bfin_read_SPT1_RX() bfin_read16(SPT1_RX) +#define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val) +#define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV) +#define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val) +#define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV) +#define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val) +#define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV) +#define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val) +#define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV) +#define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val) +#define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT) +#define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val) +#define bfin_read_SPT1_MTCS0() bfin_read32(SPT1_MTCS0) +#define bfin_write_SPT1_MTCS0(val) bfin_write32(SPT1_MTCS0, val) +#define bfin_read_SPT1_MTCS1() bfin_read32(SPT1_MTCS1) +#define bfin_write_SPT1_MTCS1(val) bfin_write32(SPT1_MTCS1, val) +#define bfin_read_SPT1_MTCS2() bfin_read32(SPT1_MTCS2) +#define bfin_write_SPT1_MTCS2(val) bfin_write32(SPT1_MTCS2, val) +#define bfin_read_SPT1_MTCS3() bfin_read32(SPT1_MTCS3) +#define bfin_write_SPT1_MTCS3(val) bfin_write32(SPT1_MTCS3, val) +#define bfin_read_SPT1_MRCS0() bfin_read32(SPT1_MRCS0) +#define bfin_write_SPT1_MRCS0(val) bfin_write32(SPT1_MRCS0, val) +#define bfin_read_SPT1_MRCS1() bfin_read32(SPT1_MRCS1) +#define bfin_write_SPT1_MRCS1(val) bfin_write32(SPT1_MRCS1, val) +#define bfin_read_SPT1_MRCS2() bfin_read32(SPT1_MRCS2) +#define bfin_write_SPT1_MRCS2(val) bfin_write32(SPT1_MRCS2, val) +#define bfin_read_SPT1_MRCS3() bfin_read32(SPT1_MRCS3) +#define bfin_write_SPT1_MRCS3(val) bfin_write32(SPT1_MRCS3, val) +#define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1) +#define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val) +#define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2) +#define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val) +#define bfin_read_SPT1_CHNL() bfin_read16(SPT1_CHNL) +#define bfin_write_SPT1_CHNL(val) bfin_write16(SPT1_CHNL, val) +#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) +#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) +#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) +#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) +#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) +#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) +#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) +#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) +#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) +#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) +#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) +#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) +#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) +#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) +#define bfin_read_TBUF() bfin_readPTR(TBUF) +#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) +#define bfin_read_PFCTL() bfin_read32(PFCTL) +#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) +#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) +#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) +#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) +#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) +#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) +#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) +#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) +#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) +#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) +#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) +#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) +#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) +#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) +#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) +#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) +#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) +#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) +#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) +#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) +#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) +#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) +#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) +#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) +#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) +#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) +#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) +#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) +#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) +#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D, val) +#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) +#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val) +#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) +#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val) +#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) +#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T, val) +#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) +#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D, val) +#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) +#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val) +#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) +#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val) +#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) +#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T, val) +#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) +#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val) +#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) +#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val) +#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) +#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val) +#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) +#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val) +#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) +#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN, val) +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) +#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) +#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) +#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) +#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) +#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) +#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) +#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) +#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) +#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) +#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) +#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) #endif /* __BFIN_CDEF_ADSP_BF531_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_def.h b/arch/blackfin/include/asm/mach-bf533/BF531_def.h index d7278e5..5d61972 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF531_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF531_def.h @@ -8,8 +8,433 @@ #include "../mach-common/ADSP-EDN-core_def.h" -#include "../mach-common/ADSP-EDN-extended_def.h" +#define MDMAFLX0_DMACNFG_D 0xFFC00E08 +#define MDMAFLX0_XCOUNT_D 0xFFC00E10 +#define MDMAFLX0_XMODIFY_D 0xFFC00E14 +#define MDMAFLX0_YCOUNT_D 0xFFC00E18 +#define MDMAFLX0_YMODIFY_D 0xFFC00E1C +#define MDMAFLX0_IRQSTAT_D 0xFFC00E28 +#define MDMAFLX0_PMAP_D 0xFFC00E2C +#define MDMAFLX0_CURXCOUNT_D 0xFFC00E30 +#define MDMAFLX0_CURYCOUNT_D 0xFFC00E38 +#define MDMAFLX0_DMACNFG_S 0xFFC00E48 +#define MDMAFLX0_XCOUNT_S 0xFFC00E50 +#define MDMAFLX0_XMODIFY_S 0xFFC00E54 +#define MDMAFLX0_YCOUNT_S 0xFFC00E58 +#define MDMAFLX0_YMODIFY_S 0xFFC00E5C +#define MDMAFLX0_IRQSTAT_S 0xFFC00E68 +#define MDMAFLX0_PMAP_S 0xFFC00E6C +#define MDMAFLX0_CURXCOUNT_S 0xFFC00E70 +#define MDMAFLX0_CURYCOUNT_S 0xFFC00E78 +#define MDMAFLX1_DMACNFG_D 0xFFC00E88 +#define MDMAFLX1_XCOUNT_D 0xFFC00E90 +#define MDMAFLX1_XMODIFY_D 0xFFC00E94 +#define MDMAFLX1_YCOUNT_D 0xFFC00E98 +#define MDMAFLX1_YMODIFY_D 0xFFC00E9C +#define MDMAFLX1_IRQSTAT_D 0xFFC00EA8 +#define MDMAFLX1_PMAP_D 0xFFC00EAC +#define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0 +#define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8 +#define MDMAFLX1_DMACNFG_S 0xFFC00EC8 +#define MDMAFLX1_XCOUNT_S 0xFFC00ED0 +#define MDMAFLX1_XMODIFY_S 0xFFC00ED4 +#define MDMAFLX1_YCOUNT_S 0xFFC00ED8 +#define MDMAFLX1_YMODIFY_S 0xFFC00EDC +#define MDMAFLX1_IRQSTAT_S 0xFFC00EE8 +#define MDMAFLX1_PMAP_S 0xFFC00EEC +#define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0 +#define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8 +#define DMAFLX0_DMACNFG 0xFFC00C08 +#define DMAFLX0_XCOUNT 0xFFC00C10 +#define DMAFLX0_XMODIFY 0xFFC00C14 +#define DMAFLX0_YCOUNT 0xFFC00C18 +#define DMAFLX0_YMODIFY 0xFFC00C1C +#define DMAFLX0_IRQSTAT 0xFFC00C28 +#define DMAFLX0_PMAP 0xFFC00C2C +#define DMAFLX0_CURXCOUNT 0xFFC00C30 +#define DMAFLX0_CURYCOUNT 0xFFC00C38 +#define DMAFLX1_DMACNFG 0xFFC00C48 +#define DMAFLX1_XCOUNT 0xFFC00C50 +#define DMAFLX1_XMODIFY 0xFFC00C54 +#define DMAFLX1_YCOUNT 0xFFC00C58 +#define DMAFLX1_YMODIFY 0xFFC00C5C +#define DMAFLX1_IRQSTAT 0xFFC00C68 +#define DMAFLX1_PMAP 0xFFC00C6C +#define DMAFLX1_CURXCOUNT 0xFFC00C70 +#define DMAFLX1_CURYCOUNT 0xFFC00C78 +#define DMAFLX2_DMACNFG 0xFFC00C88 +#define DMAFLX2_XCOUNT 0xFFC00C90 +#define DMAFLX2_XMODIFY 0xFFC00C94 +#define DMAFLX2_YCOUNT 0xFFC00C98 +#define DMAFLX2_YMODIFY 0xFFC00C9C +#define DMAFLX2_IRQSTAT 0xFFC00CA8 +#define DMAFLX2_PMAP 0xFFC00CAC +#define DMAFLX2_CURXCOUNT 0xFFC00CB0 +#define DMAFLX2_CURYCOUNT 0xFFC00CB8 +#define DMAFLX3_DMACNFG 0xFFC00CC8 +#define DMAFLX3_XCOUNT 0xFFC00CD0 +#define DMAFLX3_XMODIFY 0xFFC00CD4 +#define DMAFLX3_YCOUNT 0xFFC00CD8 +#define DMAFLX3_YMODIFY 0xFFC00CDC +#define DMAFLX3_IRQSTAT 0xFFC00CE8 +#define DMAFLX3_PMAP 0xFFC00CEC +#define DMAFLX3_CURXCOUNT 0xFFC00CF0 +#define DMAFLX3_CURYCOUNT 0xFFC00CF8 +#define DMAFLX4_DMACNFG 0xFFC00D08 +#define DMAFLX4_XCOUNT 0xFFC00D10 +#define DMAFLX4_XMODIFY 0xFFC00D14 +#define DMAFLX4_YCOUNT 0xFFC00D18 +#define DMAFLX4_YMODIFY 0xFFC00D1C +#define DMAFLX4_IRQSTAT 0xFFC00D28 +#define DMAFLX4_PMAP 0xFFC00D2C +#define DMAFLX4_CURXCOUNT 0xFFC00D30 +#define DMAFLX4_CURYCOUNT 0xFFC00D38 +#define DMAFLX5_DMACNFG 0xFFC00D48 +#define DMAFLX5_XCOUNT 0xFFC00D50 +#define DMAFLX5_XMODIFY 0xFFC00D54 +#define DMAFLX5_YCOUNT 0xFFC00D58 +#define DMAFLX5_YMODIFY 0xFFC00D5C +#define DMAFLX5_IRQSTAT 0xFFC00D68 +#define DMAFLX5_PMAP 0xFFC00D6C +#define DMAFLX5_CURXCOUNT 0xFFC00D70 +#define DMAFLX5_CURYCOUNT 0xFFC00D78 +#define DMAFLX6_DMACNFG 0xFFC00D88 +#define DMAFLX6_XCOUNT 0xFFC00D90 +#define DMAFLX6_XMODIFY 0xFFC00D94 +#define DMAFLX6_YCOUNT 0xFFC00D98 +#define DMAFLX6_YMODIFY 0xFFC00D9C +#define DMAFLX6_IRQSTAT 0xFFC00DA8 +#define DMAFLX6_PMAP 0xFFC00DAC +#define DMAFLX6_CURXCOUNT 0xFFC00DB0 +#define DMAFLX6_CURYCOUNT 0xFFC00DB8 +#define DMAFLX7_DMACNFG 0xFFC00DC8 +#define DMAFLX7_XCOUNT 0xFFC00DD0 +#define DMAFLX7_XMODIFY 0xFFC00DD4 +#define DMAFLX7_YCOUNT 0xFFC00DD8 +#define DMAFLX7_YMODIFY 0xFFC00DDC +#define DMAFLX7_IRQSTAT 0xFFC00DE8 +#define DMAFLX7_PMAP 0xFFC00DEC +#define DMAFLX7_CURXCOUNT 0xFFC00DF0 +#define DMAFLX7_CURYCOUNT 0xFFC00DF8 +#define TIMER0_CONFIG 0xFFC00600 +#define TIMER0_COUNTER 0xFFC00604 +#define TIMER0_PERIOD 0xFFC00608 +#define TIMER0_WIDTH 0xFFC0060C +#define TIMER1_CONFIG 0xFFC00610 +#define TIMER1_COUNTER 0xFFC00614 +#define TIMER1_PERIOD 0xFFC00618 +#define TIMER1_WIDTH 0xFFC0061C +#define TIMER2_CONFIG 0xFFC00620 +#define TIMER2_COUNTER 0xFFC00624 +#define TIMER2_PERIOD 0xFFC00628 +#define TIMER2_WIDTH 0xFFC0062C +#define TIMER_ENABLE 0xFFC00640 +#define TIMER_DISABLE 0xFFC00644 +#define TIMER_STATUS 0xFFC00648 +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ +#define UART_THR 0xFFC00400 /* Transmit Holding */ +#define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */ +#define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */ +#define UART_IER 0xFFC00404 +#define UART_IIR 0xFFC00408 +#define UART_LCR 0xFFC0040C +#define UART_MCR 0xFFC00410 +#define UART_LSR 0xFFC00414 +#define UART_SCR 0xFFC0041C +#define UART_RBR 0xFFC00400 /* Receive Buffer */ +#define UART_GCTL 0xFFC00424 +#define SPT0_TX_CONFIG0 0xFFC00800 +#define SPT0_TX_CONFIG1 0xFFC00804 +#define SPT0_RX_CONFIG0 0xFFC00820 +#define SPT0_RX_CONFIG1 0xFFC00824 +#define SPT0_TX 0xFFC00810 +#define SPT0_RX 0xFFC00818 +#define SPT0_TSCLKDIV 0xFFC00808 +#define SPT0_RSCLKDIV 0xFFC00828 +#define SPT0_TFSDIV 0xFFC0080C +#define SPT0_RFSDIV 0xFFC0082C +#define SPT0_STAT 0xFFC00830 +#define SPT0_MTCS0 0xFFC00840 +#define SPT0_MTCS1 0xFFC00844 +#define SPT0_MTCS2 0xFFC00848 +#define SPT0_MTCS3 0xFFC0084C +#define SPT0_MRCS0 0xFFC00850 +#define SPT0_MRCS1 0xFFC00854 +#define SPT0_MRCS2 0xFFC00858 +#define SPT0_MRCS3 0xFFC0085C +#define SPT0_MCMC1 0xFFC00838 +#define SPT0_MCMC2 0xFFC0083C +#define SPT0_CHNL 0xFFC00834 +#define SPT1_TX_CONFIG0 0xFFC00900 +#define SPT1_TX_CONFIG1 0xFFC00904 +#define SPT1_RX_CONFIG0 0xFFC00920 +#define SPT1_RX_CONFIG1 0xFFC00924 +#define SPT1_TX 0xFFC00910 +#define SPT1_RX 0xFFC00918 +#define SPT1_TSCLKDIV 0xFFC00908 +#define SPT1_RSCLKDIV 0xFFC00928 +#define SPT1_TFSDIV 0xFFC0090C +#define SPT1_RFSDIV 0xFFC0092C +#define SPT1_STAT 0xFFC00930 +#define SPT1_MTCS0 0xFFC00940 +#define SPT1_MTCS1 0xFFC00944 +#define SPT1_MTCS2 0xFFC00948 +#define SPT1_MTCS3 0xFFC0094C +#define SPT1_MRCS0 0xFFC00950 +#define SPT1_MRCS1 0xFFC00954 +#define SPT1_MRCS2 0xFFC00958 +#define SPT1_MRCS3 0xFFC0095C +#define SPT1_MCMC1 0xFFC00938 +#define SPT1_MCMC2 0xFFC0093C +#define SPT1_CHNL 0xFFC00934 +#define PPI_CONTROL 0xFFC01000 +#define PPI_STATUS 0xFFC01004 +#define PPI_DELAY 0xFFC0100C +#define PPI_COUNT 0xFFC01008 +#define PPI_FRAME 0xFFC01010 +#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ +#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ +#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ +#define SYSCR 0xFFC00104 /* System Configuration register */ +#define CHIPID 0xFFC00014 +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ +#define RTC_STAT 0xFFC00300 +#define RTC_ICTL 0xFFC00304 +#define RTC_ISTAT 0xFFC00308 +#define RTC_SWCNT 0xFFC0030C +#define RTC_ALARM 0xFFC00310 +#define RTC_PREN 0xFFC00314 +#define SPI_CTL 0xFFC00500 +#define SPI_FLG 0xFFC00504 +#define SPI_STAT 0xFFC00508 +#define SPI_TDBR 0xFFC0050C +#define SPI_RDBR 0xFFC00510 +#define SPI_BAUD 0xFFC00514 +#define SPI_SHADOW 0xFFC00518 +#define FIO_FLAG_D 0xFFC00700 +#define FIO_FLAG_C 0xFFC00704 +#define FIO_FLAG_S 0xFFC00708 +#define FIO_FLAG_T 0xFFC0070C +#define FIO_MASKA_D 0xFFC00710 +#define FIO_MASKA_C 0xFFC00714 +#define FIO_MASKA_S 0xFFC00718 +#define FIO_MASKA_T 0xFFC0071C +#define FIO_MASKB_D 0xFFC00720 +#define FIO_MASKB_C 0xFFC00724 +#define FIO_MASKB_S 0xFFC00728 +#define FIO_MASKB_T 0xFFC0072C +#define FIO_DIR 0xFFC00730 +#define FIO_POLAR 0xFFC00734 +#define FIO_EDGE 0xFFC00738 +#define FIO_BOTH 0xFFC0073C +#define FIO_INEN 0xFFC00740 +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 +#define DMA0_START_ADDR 0xFFC00C04 +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 +#define DMA0_X_MODIFY 0xFFC00C14 +#define DMA0_Y_COUNT 0xFFC00C18 +#define DMA0_Y_MODIFY 0xFFC00C1C +#define DMA0_CURR_DESC_PTR 0xFFC00C20 +#define DMA0_CURR_ADDR 0xFFC00C24 +#define DMA0_IRQ_STATUS 0xFFC00C28 +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C +#define DMA0_CURR_X_COUNT 0xFFC00C30 +#define DMA0_CURR_Y_COUNT 0xFFC00C38 +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 +#define DMA1_START_ADDR 0xFFC00C44 +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 +#define DMA1_X_MODIFY 0xFFC00C54 +#define DMA1_Y_COUNT 0xFFC00C58 +#define DMA1_Y_MODIFY 0xFFC00C5C +#define DMA1_CURR_DESC_PTR 0xFFC00C60 +#define DMA1_CURR_ADDR 0xFFC00C64 +#define DMA1_IRQ_STATUS 0xFFC00C68 +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C +#define DMA1_CURR_X_COUNT 0xFFC00C70 +#define DMA1_CURR_Y_COUNT 0xFFC00C78 +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 +#define DMA2_START_ADDR 0xFFC00C84 +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 +#define DMA2_X_MODIFY 0xFFC00C94 +#define DMA2_Y_COUNT 0xFFC00C98 +#define DMA2_Y_MODIFY 0xFFC00C9C +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 +#define DMA2_CURR_ADDR 0xFFC00CA4 +#define DMA2_IRQ_STATUS 0xFFC00CA8 +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC +#define DMA2_CURR_X_COUNT 0xFFC00CB0 +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 +#define DMA3_START_ADDR 0xFFC00CC4 +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 +#define DMA3_X_MODIFY 0xFFC00CD4 +#define DMA3_Y_COUNT 0xFFC00CD8 +#define DMA3_Y_MODIFY 0xFFC00CDC +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 +#define DMA3_CURR_ADDR 0xFFC00CE4 +#define DMA3_IRQ_STATUS 0xFFC00CE8 +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC +#define DMA3_CURR_X_COUNT 0xFFC00CF0 +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 +#define DMA4_START_ADDR 0xFFC00D04 +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 +#define DMA4_X_MODIFY 0xFFC00D14 +#define DMA4_Y_COUNT 0xFFC00D18 +#define DMA4_Y_MODIFY 0xFFC00D1C +#define DMA4_CURR_DESC_PTR 0xFFC00D20 +#define DMA4_CURR_ADDR 0xFFC00D24 +#define DMA4_IRQ_STATUS 0xFFC00D28 +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C +#define DMA4_CURR_X_COUNT 0xFFC00D30 +#define DMA4_CURR_Y_COUNT 0xFFC00D38 +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 +#define DMA5_START_ADDR 0xFFC00D44 +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 +#define DMA5_X_MODIFY 0xFFC00D54 +#define DMA5_Y_COUNT 0xFFC00D58 +#define DMA5_Y_MODIFY 0xFFC00D5C +#define DMA5_CURR_DESC_PTR 0xFFC00D60 +#define DMA5_CURR_ADDR 0xFFC00D64 +#define DMA5_IRQ_STATUS 0xFFC00D68 +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C +#define DMA5_CURR_X_COUNT 0xFFC00D70 +#define DMA5_CURR_Y_COUNT 0xFFC00D78 +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 +#define DMA6_START_ADDR 0xFFC00D84 +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 +#define DMA6_X_MODIFY 0xFFC00D94 +#define DMA6_Y_COUNT 0xFFC00D98 +#define DMA6_Y_MODIFY 0xFFC00D9C +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 +#define DMA6_CURR_ADDR 0xFFC00DA4 +#define DMA6_IRQ_STATUS 0xFFC00DA8 +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC +#define DMA6_CURR_X_COUNT 0xFFC00DB0 +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 +#define DMA7_START_ADDR 0xFFC00DC4 +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 +#define DMA7_X_MODIFY 0xFFC00DD4 +#define DMA7_Y_COUNT 0xFFC00DD8 +#define DMA7_Y_MODIFY 0xFFC00DDC +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 +#define DMA7_CURR_ADDR 0xFFC00DE4 +#define DMA7_IRQ_STATUS 0xFFC00DE8 +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC +#define DMA7_CURR_X_COUNT 0xFFC00DF0 +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 +#define MDMA_D0_START_ADDR 0xFFC00E04 +#define MDMA_D0_CONFIG 0xFFC00E08 +#define MDMA_D0_X_COUNT 0xFFC00E10 +#define MDMA_D0_X_MODIFY 0xFFC00E14 +#define MDMA_D0_Y_COUNT 0xFFC00E18 +#define MDMA_D0_Y_MODIFY 0xFFC00E1C +#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 +#define MDMA_D0_CURR_ADDR 0xFFC00E24 +#define MDMA_D0_IRQ_STATUS 0xFFC00E28 +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C +#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 +#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 +#define MDMA_S0_START_ADDR 0xFFC00E44 +#define MDMA_S0_CONFIG 0xFFC00E48 +#define MDMA_S0_X_COUNT 0xFFC00E50 +#define MDMA_S0_X_MODIFY 0xFFC00E54 +#define MDMA_S0_Y_COUNT 0xFFC00E58 +#define MDMA_S0_Y_MODIFY 0xFFC00E5C +#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 +#define MDMA_S0_CURR_ADDR 0xFFC00E64 +#define MDMA_S0_IRQ_STATUS 0xFFC00E68 +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C +#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 +#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 +#define MDMA_D1_START_ADDR 0xFFC00E84 +#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00E90 +#define MDMA_D1_X_MODIFY 0xFFC00E94 +#define MDMA_D1_Y_COUNT 0xFFC00E98 +#define MDMA_D1_Y_MODIFY 0xFFC00E9C +#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 +#define MDMA_D1_CURR_ADDR 0xFFC00EA4 +#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC +#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 +#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 +#define MDMA_S1_START_ADDR 0xFFC00EC4 +#define MDMA_S1_CONFIG 0xFFC00EC8 +#define MDMA_S1_X_COUNT 0xFFC00ED0 +#define MDMA_S1_X_MODIFY 0xFFC00ED4 +#define MDMA_S1_Y_COUNT 0xFFC00ED8 +#define MDMA_S1_Y_MODIFY 0xFFC00EDC +#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 +#define MDMA_S1_CURR_ADDR 0xFFC00EE4 +#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC +#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 +#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 +#define EBIU_AMGCTL 0xFFC00A00 +#define EBIU_AMBCTL0 0xFFC00A04 +#define EBIU_AMBCTL1 0xFFC00A08 +#define EBIU_SDGCTL 0xFFC00A10 +#define EBIU_SDBCTL 0xFFC00A14 +#define EBIU_SDRRC 0xFFC00A18 +#define EBIU_SDSTAT 0xFFC00A1C +#define DMA_TC_CNT 0xFFC00B0C +#define DMA_TC_PER 0xFFC00B10 +#ifndef __BFIN_DEF_ADSP_BF533_proc__ #define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) @@ -19,5 +444,6 @@ #define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ #define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) #define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) +#endif #endif /* __BFIN_DEF_ADSP_BF531_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h index 47b48ac..09f2521 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h +++ b/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h @@ -1,14 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF532_proc__ -#define __BFIN_CDEF_ADSP_BF532_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "../mach-common/ADSP-EDN-extended_cdef.h" - - -#endif /* __BFIN_CDEF_ADSP_BF532_proc__ */ +#include "BF531_cdef.h" diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_def.h b/arch/blackfin/include/asm/mach-bf533/BF532_def.h index 86944d0..f7378b7 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF532_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF532_def.h @@ -6,10 +6,9 @@ #ifndef __BFIN_DEF_ADSP_BF532_proc__ #define __BFIN_DEF_ADSP_BF532_proc__ -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "../mach-common/ADSP-EDN-extended_def.h" +#include "BF531_def.h" +#ifndef __BFIN_DEF_ADSP_BF533_proc__ #define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) @@ -19,5 +18,6 @@ #define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ #define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) #define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) +#endif #endif /* __BFIN_DEF_ADSP_BF532_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h index f270d01..3044327 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h +++ b/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h @@ -1,14 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF533_proc__ -#define __BFIN_CDEF_ADSP_BF533_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "../mach-common/ADSP-EDN-extended_cdef.h" - - -#endif /* __BFIN_CDEF_ADSP_BF533_proc__ */ +#include "BF532_cdef.h" diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_def.h b/arch/blackfin/include/asm/mach-bf533/BF533_def.h index 17b5d7f..b77efe0 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF533_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF533_def.h @@ -6,9 +6,7 @@ #ifndef __BFIN_DEF_ADSP_BF533_proc__ #define __BFIN_DEF_ADSP_BF533_proc__ -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "../mach-common/ADSP-EDN-extended_def.h" +#include "BF532_def.h" #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) |