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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2015-03-02 16:03:46 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2015-04-29 11:19:02 +0200 |
| commit | f25f552aab2dae05cfc1996d2c09e223ed6828a0 (patch) | |
| tree | f3a2ac33e5cba65e9dcec3e90819d4b9420718f0 /arch/arm | |
| parent | e7fa7d5c732b0fea4784b77c242bf35da06ead1d (diff) | |
| download | u-boot-imx-f25f552aab2dae05cfc1996d2c09e223ed6828a0.zip u-boot-imx-f25f552aab2dae05cfc1996d2c09e223ed6828a0.tar.gz u-boot-imx-f25f552aab2dae05cfc1996d2c09e223ed6828a0.tar.bz2 | |
zynq: slcr: Disable all level shifters
Disable all level shifters before enabling
the PS-to-PL level shifters as it would
be good to disable all level shifters before
enabling the PS-to-PL in order to ensure that
it is in proper state
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/zynq/slcr.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 2521589..05f4099 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -129,11 +129,18 @@ out: void zynq_slcr_devcfg_disable(void) { + u32 reg_val; + zynq_slcr_unlock(); /* Disable AXI interface by asserting FPGA resets */ writel(0xF, &slcr_base->fpga_rst_ctrl); + /* Disable Level shifters before setting PS-PL */ + reg_val = readl(&slcr_base->lvl_shftr_en); + reg_val &= ~0xF; + writel(reg_val, &slcr_base->lvl_shftr_en); + /* Set Level Shifters DT618760 */ writel(0xA, &slcr_base->lvl_shftr_en); |