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| author | Tom Rini <trini@konsulko.com> | 2015-08-04 12:21:45 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-04 12:21:45 -0400 |
| commit | e22b1a54942d9003b10564325a34e3cf767556ce (patch) | |
| tree | f244c37d0c1089b7e1858829e275be47f6f48ede /arch/arm | |
| parent | 8889e984154f749047dc9ed3b4cd8b734dde66f2 (diff) | |
| parent | e16b604ecf5701cc0ab4437bccfd65468035740b (diff) | |
| download | u-boot-imx-e22b1a54942d9003b10564325a34e3cf767556ce.zip u-boot-imx-e22b1a54942d9003b10564325a34e3cf767556ce.tar.gz u-boot-imx-e22b1a54942d9003b10564325a34e3cf767556ce.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/cpu.c | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/config.h | 4 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 75f0d8c..8dd95d9 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -344,5 +344,13 @@ void smp_kick_all_cpus(void) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); out_be32(&gur->brrl, 0x2); + + /* + * LS1 STANDBYWFE is not captured outside the ARM module in the soc. + * So add a delay to wait bootrom execute WFE. + */ + udelay(1); + + asm volatile("sev"); } #endif diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 8675e91..a4576dd 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -10,6 +10,7 @@ #include <fsl_ddrc_version.h> #define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 64 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 @@ -63,6 +64,9 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) + /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 #define TZPCR0SIZE_BASE (TZPC_BASE) |