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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-03-18 16:41:50 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-03-24 01:45:21 +0900 |
commit | c8cc7213a5fd6e8dc3429fc1c3513b3de99e211e (patch) | |
tree | b15372261dc7ba74eec87e817c432abcdad85140 /arch/arm | |
parent | fc26b7b91d0f4ffbd67bc1bfdf0b01a5b4c53f0f (diff) | |
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ARM: uniphier: add sg_set_iectrl() function
This helper function would be useful for new SoCs with per-pin
input enable controlling, such as PH1-LD20, PH1-LD11, etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-uniphier/sg-regs.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 3a535c7..2cdc2db 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -115,6 +115,17 @@ static inline void sg_set_pinsel(unsigned pin, unsigned muxval, writel(tmp, reg); } +static inline void sg_set_iectrl(unsigned pin) +{ + unsigned bit = pin % 32; + unsigned long reg = SG_IECTRL + pin / 32 * 4; + u32 tmp; + + tmp = readl(reg); + tmp |= 1 << bit; + writel(tmp, reg); +} + #endif /* __ASSEMBLY__ */ #endif /* ARCH_SG_REGS_H */ |