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authorSiarhei Siamashka <siarhei.siamashka@gmail.com>2014-08-03 05:32:49 +0300
committerHans de Goede <hdegoede@redhat.com>2014-08-12 08:42:33 +0200
commitb8f7cb6ae31d3c2de7349e58889ed3c5a1a77c42 (patch)
treec5f03c352505b029212e72e8cdd0254397692037 /arch/arm
parent013f2d746955147439215a4939655c9ed6bdd866 (diff)
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sunxi: dram: Improve DQS gate data training error handling
The stale error status should be cleared for all sun4i/sun5i/sun7i hardware and not just for sun7i. Also there are two types of DQS gate training errors ("found no result" and "found more than one possible result"). Both are handled now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram.c2
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram.h4
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 6f98c6a..47017d2 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -357,9 +357,7 @@ static int dramc_scan_readpipe(void)
u32 reg_val;
/* data training trigger */
-#ifdef CONFIG_SUN7I
clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
-#endif
setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
/* check whether data training process has completed */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 3c29256..11e3507 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -133,7 +133,9 @@ struct dram_para {
#define DRAM_DCR_MODE_SEQ 0x0
#define DRAM_DCR_MODE_INTERLEAVE 0x1
-#define DRAM_CSR_FAILED (0x1 << 20)
+#define DRAM_CSR_DTERR (0x1 << 20)
+#define DRAM_CSR_DTIERR (0x1 << 21)
+#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
#define DRAM_DRR_TRFC(n) ((n) & 0xff)
#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)