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authorMichael Langer <michael.langer@de.bosch.com>2012-06-14 03:44:33 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:29 +0200
commit5c23712dbdeeaef84ee28a18dc23abd479a95ede (patch)
treef9207d7c9eec2b8916d2146bce78da7d0dfd1729 /arch/arm
parentf69b0653acf5482a94fa1ec9542165914e30e50c (diff)
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i.MX6 USDHC: Use the ESDHC clock
The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces support for the i.MX6Q MMC host controller USDHC. MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()). Signed-off-by: Michael Langer <michael.langer@de.bosch.com> CC: Stefano Babic <sbabic@denx.de> CC: Jason Liu <r64343@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/imx-common/speed.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/cpu/armv7/imx-common/speed.c
index 2187e8e..80989c4 100644
--- a/arch/arm/cpu/armv7/imx-common/speed.c
+++ b/arch/arm/cpu/armv7/imx-common/speed.c
@@ -35,7 +35,11 @@ DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_USDHC
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#else
gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
#endif
+#endif
return 0;
}