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authorWolfgang Denk <wd@denx.de>2010-06-30 10:10:32 +0200
committerWolfgang Denk <wd@denx.de>2010-06-30 10:10:32 +0200
commit39ddd10b046fb791f47281ffb2100be01909ad72 (patch)
treecec01ecc6502a65cbbbda406dfac23b93c093899 /arch/arm
parent55357b7846237d12aa5f07aec657c5dbfaf790ed (diff)
parent0a9463e93537a68e7246714f43fb69eca0b7b214 (diff)
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Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/arch-davinci/emac_defs.h2
-rw-r--r--arch/arm/include/asm/arch-pxa/pxa-regs.h25
2 files changed, 22 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h
index b0ec8f5..35a1585 100644
--- a/arch/arm/include/asm/arch-davinci/emac_defs.h
+++ b/arch/arm/include/asm/arch-davinci/emac_defs.h
@@ -85,7 +85,7 @@
#endif
/* PHY mask - set only those phy number bits where phy is/can be connected */
-#define EMAC_MDIO_PHY_NUM 1
+#define EMAC_MDIO_PHY_NUM CONFIG_EMAC_MDIO_PHY_NUM
#define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM)
/* Ethernet Min/Max packet size */
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index a25d4c5..cd7b7f9 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -992,10 +992,6 @@ typedef void (*ExcpHndlr) (void) ;
#define UHCHIE __REG(0x4C000068)
#define UHCHIT __REG(0x4C00006C)
-#if defined(CONFIG_CPU_MONAHANS)
-#define UP2OCR __REG(0x40600020)
-#endif
-
#define UHCHR_FSBIR (1<<0)
#define UHCHR_FHR (1<<1)
#define UHCHR_CGR (1<<2)
@@ -1015,6 +1011,24 @@ typedef void (*ExcpHndlr) (void) ;
#define UHCHIE_HBAIE (1<<8)
#define UHCHIE_RWIE (1<<7)
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+#define UP2OCR __REG(0x40600020)
+#endif
+
+#define UP2OCR_HXOE (1<<17)
+#define UP2OCR_HXS (1<<16)
+#define UP2OCR_IDON (1<<10)
+#define UP2OCR_EXSUS (1<<9)
+#define UP2OCR_EXSP (1<<8)
+#define UP2OCR_DMSTATE (1<<7)
+#define UP2OCR_VPM (1<<6)
+#define UP2OCR_DPSTATE (1<<5)
+#define UP2OCR_DPPUE (1<<4)
+#define UP2OCR_DMPDE (1<<3)
+#define UP2OCR_DPPDE (1<<2)
+#define UP2OCR_CPVPE (1<<1)
+#define UP2OCR_CPVEN (1<<0)
+
#endif
/*
@@ -2407,6 +2421,9 @@ typedef void (*ExcpHndlr) (void) ;
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */
+#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */
+#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */