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author | Tom Rini <trini@konsulko.com> | 2016-05-27 15:48:53 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2016-05-27 15:48:53 -0400 |
commit | 378f9134eba4665ea94a63653393d25418665fda (patch) | |
tree | e273a03c52e8261c0f6c401914d44a9eff442684 /arch/arm | |
parent | 9b77b19178446393fce2e74554815c17454f8da8 (diff) | |
parent | 2ed6dc83380ea2f49ec09556c14c6eddd3f5c27a (diff) | |
download | u-boot-imx-378f9134eba4665ea94a63653393d25418665fda.zip u-boot-imx-378f9134eba4665ea94a63653393d25418665fda.tar.gz u-boot-imx-378f9134eba4665ea94a63653393d25418665fda.tar.bz2 |
Merge git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/dts/rk3288-firefly.dtsi | 16 | ||||
-rw-r--r-- | arch/arm/dts/rk3288-rock2-square.dts | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 17 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 53 |
4 files changed, 87 insertions, 1 deletions
diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi index 5aec1b8..072eaa6 100644 --- a/arch/arm/dts/rk3288-firefly.dtsi +++ b/arch/arm/dts/rk3288-firefly.dtsi @@ -146,6 +146,22 @@ status = "okay"; }; +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts index 8d7446f..34073c9 100644 --- a/arch/arm/dts/rk3288-rock2-square.dts +++ b/arch/arm/dts/rk3288-rock2-square.dts @@ -111,7 +111,7 @@ }; &gmac { - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index d2690c7..8a8ca9c 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -90,6 +90,23 @@ enum { SDIO0_DIV_MASK = 0x3f, }; +/* CRU_CLKSEL21_CON */ +enum { + MAC_DIV_CON_SHIFT = 0xf, + MAC_DIV_CON_MASK = 0x1f, + + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = 1, + RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, + RMII_EXTCLK_SELECT_EXT_CLK = 1, + + EMAC_PLL_SHIFT = 0, + EMAC_PLL_MASK = 0x3, + EMAC_PLL_SELECT_NEW = 0x0, + EMAC_PLL_SELECT_CODEC = 0x1, + EMAC_PLL_SELECT_GENERAL = 0x2, +}; + /* CRU_CLKSEL25_CON */ enum { SPI1_PLL_SHIFT = 0xf, diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 0117a17..aaffd19 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -718,6 +718,40 @@ enum { MSCH0_MAINPARTIALPOP_MASK = 1, }; +/* GRF_SOC_CON1 */ +enum { + RMII_MODE_SHIFT = 0xe, + RMII_MODE_MASK = 1, + RMII_MODE = 1, + + GMAC_CLK_SEL_SHIFT = 0xc, + GMAC_CLK_SEL_MASK = 3, + GMAC_CLK_SEL_125M = 0, + GMAC_CLK_SEL_25M = 0x3, + GMAC_CLK_SEL_2_5M = 0x2, + + RMII_CLK_SEL_SHIFT = 0xb, + RMII_CLK_SEL_MASK = 1, + RMII_CLK_SEL_2_5M = 0, + RMII_CLK_SEL_25M, + + GMAC_SPEED_SHIFT = 0xa, + GMAC_SPEED_MASK = 1, + GMAC_SPEED_10M = 0, + GMAC_SPEED_100M, + + GMAC_FLOWCTRL_SHIFT = 0x9, + GMAC_FLOWCTRL_MASK = 1, + + GMAC_PHY_INTF_SEL_SHIFT = 0x6, + GMAC_PHY_INTF_SEL_MASK = 0x7, + GMAC_PHY_INTF_SEL_RGMII = 0x1, + GMAC_PHY_INTF_SEL_RMII = 0x4, + + HOST_REMAP_SHIFT = 0x5, + HOST_REMAP_MASK = 1 +}; + /* GRF_SOC_CON2 */ enum { UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd, @@ -765,4 +799,23 @@ enum { PWM_PWM = 0, }; +/* GRF_SOC_CON3 */ +enum { + RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, + RXCLK_DLY_ENA_GMAC_MASK = 1, + RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RXCLK_DLY_ENA_GMAC_ENABLE, + + TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, + TXCLK_DLY_ENA_GMAC_MASK = 1, + TXCLK_DLY_ENA_GMAC_DISABLE = 0, + TXCLK_DLY_ENA_GMAC_ENABLE, + + CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, + CLK_RX_DL_CFG_GMAC_MASK = 0x7f, + + CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, + CLK_TX_DL_CFG_GMAC_MASK = 0x7f, +}; + #endif |