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authorStefano Babic <sbabic@denx.de>2014-04-04 11:35:30 +0200
committerStefano Babic <sbabic@denx.de>2014-04-04 11:35:30 +0200
commit1cad23c5f471d695bed1e3907e30caee3c2a3056 (patch)
tree34e035df5db9b327aeae36eff9d0645a915e3177 /arch/arm
parent5dd73bc0a40a4b318195eab871a1f535aad6b43b (diff)
parent00b132bf34c5be86a108ac7fe8231ad9e97f6de4 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm into master
Conflicts: arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/config.mk25
-rw-r--r--arch/arm/cpu/arm720t/tegra-common/cpu.c5
-rw-r--r--arch/arm/cpu/arm720t/tegra114/config.mk19
-rw-r--r--arch/arm/cpu/arm720t/tegra124/config.mk7
-rw-r--r--arch/arm/cpu/arm720t/tegra124/cpu.c4
-rw-r--r--arch/arm/cpu/arm720t/tegra20/config.mk10
-rw-r--r--arch/arm/cpu/arm720t/tegra30/config.mk19
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c25
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/Makefile13
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg4
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg4
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd4
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd4
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c8
-rw-r--r--arch/arm/cpu/armv7/exynos/pinmux.c29
-rw-r--r--arch/arm/cpu/armv7/kona-common/hwinit-common.c2
-rw-r--r--arch/arm/cpu/armv7/omap-common/hwinit-common.c2
-rw-r--r--arch/arm/cpu/armv7/omap4/hwinit.c2
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c2
-rw-r--r--arch/arm/cpu/at91-common/phy.c2
-rw-r--r--arch/arm/cpu/at91-common/spl.c4
-rw-r--r--arch/arm/dts/Makefile5
-rw-r--r--arch/arm/dts/exynos4.dtsi138
-rw-r--r--arch/arm/dts/exynos4210-origen.dts45
-rw-r--r--arch/arm/dts/exynos4210-trats.dts120
-rw-r--r--arch/arm/dts/exynos4210-universal_c210.dts83
-rw-r--r--arch/arm/dts/exynos4412-trats2.dts434
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h51
-rw-r--r--arch/arm/include/asm/arch-am33xx/omap_gpmc.h48
-rw-r--r--arch/arm/include/asm/arch-am33xx/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-at91/gpio.h2
-rw-r--r--arch/arm/include/asm/arch-at91/spl.h4
-rw-r--r--arch/arm/include/asm/arch-davinci/hardware.h2
-rw-r--r--arch/arm/include/asm/arch-exynos/board.h12
-rw-r--r--arch/arm/include/asm/arch-exynos/mipi_dsim.h5
-rw-r--r--arch/arm/include/asm/arch-exynos/mmc.h7
-rw-r--r--arch/arm/include/asm/arch-kirkwood/config.h2
-rw-r--r--arch/arm/include/asm/arch-mb86r0x/hardware.h2
-rw-r--r--arch/arm/include/asm/arch-omap3/cpu.h54
-rw-r--r--arch/arm/include/asm/arch-omap3/mem.h10
-rw-r--r--arch/arm/include/asm/arch-omap3/omap_gpmc.h36
-rw-r--r--arch/arm/include/asm/arch-omap3/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-omap4/cpu.h45
-rw-r--r--arch/arm/include/asm/arch-omap4/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-omap5/cpu.h45
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-tegra/pmc.h11
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra.h5
-rw-r--r--arch/arm/include/asm/arch-tegra114/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-tegra124/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-tegra20/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-tegra30/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-tnetv107x/hardware.h2
-rw-r--r--arch/arm/include/asm/arch-zynq/sys_proto.h1
-rw-r--r--arch/arm/include/asm/omap_elm.h77
-rw-r--r--arch/arm/include/asm/omap_gpmc.h87
-rw-r--r--arch/arm/include/asm/sizes.h39
-rw-r--r--arch/arm/lib/Makefile13
-rw-r--r--arch/arm/lib/board.c6
59 files changed, 1007 insertions, 590 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 5bd3961..4502fd9 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -5,7 +5,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
-CROSS_COMPILE ?= arm-linux-
+ifeq ($(CROSS_COMPILE),)
+CROSS_COMPILE := arm-linux-
+endif
ifndef CONFIG_STANDALONE_LOAD_ADDR
ifneq ($(CONFIG_OMAP_COMMON),)
@@ -39,7 +41,17 @@ endif
# Only test once
ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+archprepare: checkthumb
+
+checkthumb:
+ @if test "$(call cc-version)" -lt "0404"; then \
+ echo -n '*** Your GCC does not produce working '; \
+ echo 'binaries in THUMB mode.'; \
+ echo '*** Your board is configured for THUMB mode.'; \
+ false; \
+ fi
+endif
endif
# Try if EABI is supported, else fall back to old API,
@@ -67,13 +79,8 @@ ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
# times. Also, the prefix needs to be different based on whether
# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
# before adding the correct one.
-ifdef CONFIG_SPL_BUILD
-PLATFORM_LIBS := $(SPLTREE)/arch/arm/lib/eabi_compat.o \
- $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
-else
-PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \
- $(filter-out %/arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
-endif
+PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \
+ $(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
endif
# needed for relocation
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 2c5cd63..168f525 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -378,8 +378,7 @@ void clock_enable_coresight(int enable)
void halt_avp(void)
{
for (;;) {
- writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
- | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
- FLOW_CTLR_HALT_COP_EVENTS);
+ writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
+ FLOW_CTLR_HALT_COP_EVENTS);
}
}
diff --git a/arch/arm/cpu/arm720t/tegra114/config.mk b/arch/arm/cpu/arm720t/tegra114/config.mk
deleted file mode 100644
index 7947b50..0000000
--- a/arch/arm/cpu/arm720t/tegra114/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra124/config.mk b/arch/arm/cpu/arm720t/tegra124/config.mk
deleted file mode 100644
index 5e10701..0000000
--- a/arch/arm/cpu/arm720t/tegra124/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2010-2013
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#/
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
index c03aaf1..97f5928 100644
--- a/arch/arm/cpu/arm720t/tegra124/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -252,8 +252,8 @@ void start_cpu(u32 reset_vector)
tegra124_init_clocks();
/* Set power-gating timer multiplier */
- clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
- setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+ writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
+ &pmc->pmc_pwrgate_timer_mult);
enable_cpu_power_rail();
enable_cpu_clocks();
diff --git a/arch/arm/cpu/arm720t/tegra20/config.mk b/arch/arm/cpu/arm720t/tegra20/config.mk
deleted file mode 100644
index e073345..0000000
--- a/arch/arm/cpu/arm720t/tegra20/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010,2011
-# NVIDIA Corporation <www.nvidia.com>
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra30/config.mk b/arch/arm/cpu/arm720t/tegra30/config.mk
deleted file mode 100644
index 2388c56..0000000
--- a/arch/arm/cpu/arm720t/tegra30/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
index 99a3913..6b51d5f 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -143,6 +143,31 @@ void at91_spi1_hw_init(unsigned long cs_mask)
}
#endif
+#if defined(CONFIG_GENERIC_ATMEL_MCI)
+void at91_mci_hw_init(void)
+{
+ /* Enable mci clock */
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
+
+ at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
+
+#if defined(CONFIG_ATMEL_MCI_PORTB)
+ at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */
+ at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */
+#else
+ at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */
+ at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */
+#endif
+}
+#endif
+
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 152546e..1eee661 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -14,11 +14,12 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
endif
# Specify the target for use in elftosb call
-MKIMAGE_TARGET-$(CONFIG_MX23) = mx23
-MKIMAGE_TARGET-$(CONFIG_MX28) = mx28
+MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
+MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
-$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg
- sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
+quiet_cmd_mkimage_mxs = UIMAGE $@
+cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg
- $(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@
+u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage_mxs)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
index 70abfbc..55510e9 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
@@ -1,6 +1,6 @@
SECTION 0x0 BOOTABLE
TAG LAST
- LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin
+ LOAD 0x1000 spl/u-boot-spl.bin
CALL 0x1000 0x0
- LOAD 0x40002000 OBJTREE/u-boot.bin
+ LOAD 0x40002000 u-boot.bin
CALL 0x40002000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
index e98c97b..bb78cb0 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
@@ -1,8 +1,8 @@
SECTION 0x0 BOOTABLE
TAG LAST
- LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin
+ LOAD 0x1000 spl/u-boot-spl.bin
LOAD IVT 0x8000 0x1000
CALL HAB 0x8000 0x0
- LOAD 0x40002000 OBJTREE/u-boot.bin
+ LOAD 0x40002000 u-boot.bin
LOAD IVT 0x8000 0x40002000
CALL HAB 0x8000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
index 8b6c30e..3a51879 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
@@ -4,8 +4,8 @@ options {
}
sources {
- u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
- u_boot="OBJTREE/u-boot.bin";
+ u_boot_spl="spl/u-boot-spl.bin";
+ u_boot="u-boot.bin";
}
section (0) {
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
index a5fa648..c60615a 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
@@ -1,6 +1,6 @@
sources {
- u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
- u_boot="OBJTREE/u-boot.bin";
+ u_boot_spl="spl/u-boot-spl.bin";
+ u_boot="u-boot.bin";
}
section (0) {
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 2b15a64..fb44cc8 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -202,6 +202,7 @@ static void watchdog_disable(void)
}
#endif
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
void s_init(void)
{
/*
@@ -220,22 +221,19 @@ void s_init(void)
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
watchdog_disable();
timer_init();
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
-#endif
#ifdef CONFIG_NOR_BOOT
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
-#else
+#elif defined(CONFIG_SPL_BUILD)
gd = &gdata;
preloader_console_init();
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
prcm_init();
set_mux_conf_regs();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
@@ -243,8 +241,8 @@ void s_init(void)
rtc32k_enable();
#endif
sdram_init();
-#endif
}
+#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 645c497..9edb475 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -39,6 +39,9 @@ static void exynos5_uart_config(int peripheral)
start = 4;
count = 2;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
@@ -74,6 +77,9 @@ static void exynos5420_uart_config(int peripheral)
start = 4;
count = 2;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
}
for (i = start; i < start + count; i++) {
@@ -110,6 +116,9 @@ static int exynos5_mmc_config(int peripheral, int flags)
bank = &gpio1->c4;
bank_ext = NULL;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
debug("SDMMC device %d does not support 8bit mode",
@@ -683,6 +692,9 @@ static void exynos4_uart_config(int peripheral)
start = 4;
count = 2;
break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
@@ -741,6 +753,21 @@ int exynos_pinmux_config(int peripheral, int flags)
}
#ifdef CONFIG_OF_CONTROL
+static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
+{
+ int err;
+ u32 cell[3];
+
+ err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+ ARRAY_SIZE(cell));
+ if (err) {
+ debug(" invalid peripheral id\n");
+ return PERIPH_ID_NONE;
+ }
+
+ return cell[1];
+}
+
static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
{
int err;
@@ -758,6 +785,8 @@ int pinmux_decode_periph_id(const void *blob, int node)
{
if (cpu_is_exynos5())
return exynos5_pinmux_decode_periph_id(blob, node);
+ else if (cpu_is_exynos4())
+ return exynos4_pinmux_decode_periph_id(blob, node);
else
return PERIPH_ID_NONE;
}
diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
index f8b1e06..2b3a840 100644
--- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
@@ -5,7 +5,7 @@
*/
#include <common.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index ade744e..8ebc0ce 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -14,7 +14,7 @@
#include <common.h>
#include <spl.h>
#include <asm/arch/sys_proto.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index b0598a0..db16548 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -15,7 +15,7 @@
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/emif.h>
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 737d23c..93feb16 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -17,7 +17,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c
index 3b6c60c..2cba716 100644
--- a/arch/arm/cpu/at91-common/phy.c
+++ b/arch/arm/cpu/at91-common/phy.c
@@ -14,7 +14,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <watchdog.h>
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
index 37c0cc4..7f4debb 100644
--- a/arch/arm/cpu/at91-common/spl.c
+++ b/arch/arm/cpu/at91-common/spl.c
@@ -52,6 +52,10 @@ u32 spl_boot_device(void)
{
#ifdef CONFIG_SYS_USE_MMC
return BOOT_DEVICE_MMC1;
+#elif CONFIG_SYS_USE_NANDFLASH
+ return BOOT_DEVICE_NAND;
+#elif CONFIG_SYS_USE_SERIALFLASH
+ return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_NONE;
}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6acd861..2c3c773 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1,3 +1,8 @@
+dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
+ exynos4210-universal_c210.dtb \
+ exynos4210-trats.dtb \
+ exynos4412-trats2.dtb
+
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-smdk5250.dtb \
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
new file mode 100644
index 0000000..71dc7eb
--- /dev/null
+++ b/arch/arm/dts/exynos4.dtsi
@@ -0,0 +1,138 @@
+/*
+ * Samsung's Exynos4 SoC common device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ serial@13800000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13800000 0x3c>;
+ id = <0>;
+ };
+
+ serial@13810000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13810000 0x3c>;
+ id = <1>;
+ };
+
+ serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x3c>;
+ id = <2>;
+ };
+
+ serial@13830000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13830000 0x3c>;
+ id = <3>;
+ };
+
+ serial@13840000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13840000 0x3c>;
+ id = <4>;
+ };
+
+ i2c@13860000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <0 0 0>;
+ };
+
+ i2c@13870000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <1 1 0>;
+ };
+
+ i2c@13880000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <2 2 0>;
+ };
+
+ i2c@13890000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <3 3 0>;
+ };
+
+ i2c@138a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <4 4 0>;
+ };
+
+ i2c@138b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <5 5 0>;
+ };
+
+ i2c@138c0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <6 6 0>;
+ };
+
+ i2c@138d0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ interrupts = <7 7 0>;
+ };
+
+ sdhci@12510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12510000 0x1000>;
+ interrupts = <0 75 0>;
+ };
+
+ sdhci@12520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12520000 0x1000>;
+ interrupts = <0 76 0>;
+ };
+
+ sdhci@12530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12530000 0x1000>;
+ interrupts = <0 77 0>;
+ };
+
+ sdhci@12540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-mmc";
+ reg = <0x12540000 0x1000>;
+ interrupts = <0 78 0>;
+ };
+
+ gpio: gpio {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts
new file mode 100644
index 0000000..5c9d2ae
--- /dev/null
+++ b/arch/arm/dts/exynos4210-origen.dts
@@ -0,0 +1,45 @@
+/*
+ * Samsung's Exynos4210 based Origen board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Insignal Origen evaluation board based on Exynos4210";
+ compatible = "insignal,origen", "samsung,exynos4210";
+
+ chosen {
+ bootargs ="";
+ };
+
+ aliases {
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ sdhci@12510000 {
+ status = "disabled";
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x2008002 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+}; \ No newline at end of file
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
new file mode 100644
index 0000000..992e023
--- /dev/null
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -0,0 +1,120 @@
+/*
+ * Samsung's Exynos4210 based Trats board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Samsung Trats based on Exynos4210";
+ compatible = "samsung,trats", "samsung,exynos4210";
+
+ config {
+ samsung,dsim-device-name = "s6e8ax0";
+ };
+
+ aliases {
+ i2c0 = "/i2c@13860000";
+ i2c1 = "/i2c@13870000";
+ i2c2 = "/i2c@13880000";
+ i2c3 = "/i2c@13890000";
+ i2c4 = "/i2c@138a0000";
+ i2c5 = "/i2c@138b0000";
+ i2c6 = "/i2c@138c0000";
+ i2c7 = "/i2c@138d0000";
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc0 = "sdhci@12510000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x11c00000 0xa4>;
+
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <720>;
+ samsung,vl-row = <1280>;
+ samsung,vl-width = <720>;
+ samsung,vl-height = <1280>;
+
+ samsung,vl-clkp = <0>;
+ samsung,vl-oep = <0>;
+ samsung,vl-hsp = <1>;
+ samsung,vl-vsp = <1>;
+ samsung,vl-dp = <1>;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <5>;
+ samsung,vl-hbpd = <10>;
+ samsung,vl-hfpd = <10>;
+ samsung,vl-vspw = <2>;
+ samsung,vl-vbpd = <1>;
+ samsung,vl-vfpd = <13>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,power-on-delay = <30>;
+ samsung,interface-mode = <1>;
+ samsung,mipi-enabled = <1>;
+ samsung,dp-enabled;
+ samsung,dual-lcd-enabled;
+
+ samsung,logo-on = <1>;
+ samsung,resolution = <0>;
+ samsung,rgb-mode = <0>;
+ };
+
+ mipidsi@11c80000 {
+ compatible = "samsung,exynos-mipi-dsi";
+ reg = <0x11c80000 0x5c>;
+
+ samsung,dsim-config-e-interface = <1>;
+ samsung,dsim-config-e-virtual-ch = <0>;
+ samsung,dsim-config-e-pixel-format = <7>;
+ samsung,dsim-config-e-burst-mode = <1>;
+ samsung,dsim-config-e-no-data-lane = <3>;
+ samsung,dsim-config-e-byte-clk = <0>;
+ samsung,dsim-config-hfp = <1>;
+
+ samsung,dsim-config-p = <3>;
+ samsung,dsim-config-m = <120>;
+ samsung,dsim-config-s = <1>;
+
+ samsung,dsim-config-pll-stable-time = <500>;
+ samsung,dsim-config-esc-clk = <20000000>;
+ samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+ samsung,dsim-config-bta-timeout = <0xff>;
+ samsung,dsim-config-rx-timeout = <0xffff>;
+
+ samsung,dsim-device-id = <0xffffffff>;
+ samsung,dsim-device-bus-id = <0>;
+
+ samsung,dsim-device-reverse-panel = <1>;
+ };
+
+ sdhci@12510000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ pwr-gpios = <&gpio 0x2008002 0>;
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x20c6004 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+}; \ No newline at end of file
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
new file mode 100644
index 0000000..1cdd981
--- /dev/null
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -0,0 +1,83 @@
+/*
+ * Samsung's Exynos4210 based Universal C210 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Samsung Universal C210 based on Exynos4210 rev0";
+ compatible = "samsung,universal_c210", "samsung,exynos4210";
+
+ aliases {
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc0 = "sdhci@12510000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ sdhci@12510000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ pwr-gpios = <&gpio 0x2008002 0>;
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x20c6004 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x11c00000 0xa4>;
+
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <480>;
+ samsung,vl-row = <800>;
+ samsung,vl-width = <480>;
+ samsung,vl-height = <800>;
+
+ samsung,vl-clkp = <0>;
+ samsung,vl-oep = <0>;
+ samsung,vl-hsp = <1>;
+ samsung,vl-vsp = <1>;
+ samsung,vl-dp = <1>;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <2>;
+ samsung,vl-hbpd = <16>;
+ samsung,vl-hfpd = <16>;
+ samsung,vl-vspw = <2>;
+ samsung,vl-vbpd = <8>;
+ samsung,vl-vfpd = <8>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,pclk_name = <1>;
+ samsung,sclk_div = <1>;
+
+ samsung,winid = <0>;
+ samsung,power-on-delay = <10000>;
+ samsung,interface-mode = <1>;
+ samsung,mipi-enabled = <0>;
+ samsung,dp-enabled;
+ samsung,dual-lcd-enabled;
+
+ samsung,logo-on = <1>;
+ samsung,resolution = <0>;
+ samsung,rgb-mode = <0>;
+ };
+};
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts
new file mode 100644
index 0000000..7d32067
--- /dev/null
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -0,0 +1,434 @@
+/*
+ * Samsung's Exynos4412 based Trats2 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+ model = "Samsung Trats2 based on Exynos4412";
+ compatible = "samsung,trats2", "samsung,exynos4412";
+
+ config {
+ samsung,dsim-device-name = "s6e8ax0";
+ };
+
+ aliases {
+ i2c0 = "/i2c@13860000";
+ i2c1 = "/i2c@13870000";
+ i2c2 = "/i2c@13880000";
+ i2c3 = "/i2c@13890000";
+ i2c4 = "/i2c@138a0000";
+ i2c5 = "/i2c@138b0000";
+ i2c6 = "/i2c@138c0000";
+ i2c7 = "/i2c@138d0000";
+ serial0 = "/serial@13800000";
+ console = "/serial@13820000";
+ mmc0 = "sdhci@12510000";
+ mmc2 = "sdhci@12530000";
+ };
+
+ i2c@138d0000 {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ max77686_pmic@09 {
+ compatible = "maxim,max77686_pmic";
+ interrupts = <7 0>;
+ reg = <0x09 0 0>;
+ #clock-cells = <1>;
+
+ voltage-regulators {
+ ldo1_reg: ldo1 {
+ regulator-compatible = "LDO1";
+ regulator-name = "VALIVE_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-compatible = "LDO2";
+ regulator-name = "VM1M2_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-compatible = "LDO3";
+ regulator-name = "VCC_1.8V_AP";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-compatible = "LDO4";
+ regulator-name = "VCC_2.8V_AP";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-compatible = "LDO5";
+ regulator-name = "VCC_1.8V_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-compatible = "LDO6";
+ regulator-name = "VMPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-compatible = "LDO7";
+ regulator-name = "VPLL_1.0V_AP";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-mem-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-compatible = "LDO8";
+ regulator-name = "VMIPI_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-compatible = "LDO9";
+ regulator-name = "CAM_ISP_MIPI_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo10_reg: ldo10 {
+ regulator-compatible = "LDO10";
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo11_reg: ldo11 {
+ regulator-compatible = "LDO11";
+ regulator-name = "VABB1_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo12_reg: ldo12 {
+ regulator-compatible = "LDO12";
+ regulator-name = "VUOTG_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-off;
+ };
+
+ ldo13_reg: ldo13 {
+ regulator-compatible = "LDO13";
+ regulator-name = "NFC_AVDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo14_reg: ldo14 {
+ regulator-compatible = "LDO14";
+ regulator-name = "VABB2_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo15_reg: ldo15 {
+ regulator-compatible = "LDO15";
+ regulator-name = "VHSIC_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-mem-off;
+ };
+
+ ldo16_reg: ldo16 {
+ regulator-compatible = "LDO16";
+ regulator-name = "VHSIC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-off;
+ };
+
+ ldo17_reg: ldo17 {
+ regulator-compatible = "LDO17";
+ regulator-name = "CAM_SENSOR_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-idle;
+ };
+
+ ldo18_reg: ldo18 {
+ regulator-compatible = "LDO18";
+ regulator-name = "CAM_ISP_SEN_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo19_reg: ldo19 {
+ regulator-compatible = "LDO19";
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo20_reg: ldo20 {
+ regulator-compatible = "LDO20";
+ regulator-name = "VDDQ_PRE_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo21_reg: ldo21 {
+ regulator-compatible = "LDO21";
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo22_reg: ldo22 {
+ regulator-compatible = "LDO22";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ ldo23_reg: ldo23 {
+ regulator-compatible = "LDO23";
+ regulator-name = "TSP_AVDD_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-mem-idle;
+ };
+
+ ldo24_reg: ldo24 {
+ regulator-compatible = "LDO24";
+ regulator-name = "TSP_VDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-mem-idle;
+ };
+
+ ldo25_reg: ldo25 {
+ regulator-compatible = "LDO25";
+ regulator-name = "LCD_VCC_3.3V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-mem-idle;
+ };
+
+ ldo26_reg: ldo26 {
+ regulator-compatible = "LDO26";
+ regulator-name = "MOTOR_VCC_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-mem-idle;
+ };
+
+ buck1_reg: buck1 {
+ regulator-compatible = "BUCK1";
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck2_reg: buck2 {
+ regulator-compatible = "BUCK2";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck3_reg: buck3 {
+ regulator-compatible = "BUCK3";
+ regulator-name = "vdd_int";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck4_reg: buck4 {
+ regulator-compatible = "BUCK4";
+ regulator-name = "vdd_g3d";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-mem-off;
+ };
+
+ buck5_reg: buck5 {
+ regulator-compatible = "BUCK5";
+ regulator-name = "VMEM_1.2V_AP";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck6_reg: buck6 {
+ regulator-compatible = "BUCK6";
+ regulator-name = "VCC_SUB_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ buck7_reg: buck7 {
+ regulator-compatible = "BUCK7";
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ buck8_reg: buck8 {
+ regulator-compatible = "BUCK8";
+ regulator-name = "VMEM_VDDF_3.0V";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-mem-off;
+ };
+
+ buck9_reg: buck9 {
+ regulator-compatible = "BUCK9";
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-mem-off;
+ };
+ };
+ };
+ };
+
+ fimd@11c00000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x11c00000 0xa4>;
+
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <720>;
+ samsung,vl-row = <1280>;
+ samsung,vl-width = <720>;
+ samsung,vl-height = <1280>;
+
+ samsung,vl-clkp = <0>;
+ samsung,vl-oep = <0>;
+ samsung,vl-hsp = <1>;
+ samsung,vl-vsp = <1>;
+ samsung,vl-dp = <1>;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <5>;
+ samsung,vl-hbpd = <10>;
+ samsung,vl-hfpd = <10>;
+ samsung,vl-vspw = <2>;
+ samsung,vl-vbpd = <1>;
+ samsung,vl-vfpd = <13>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <0>;
+ samsung,power-on-delay = <30>;
+ samsung,interface-mode = <1>;
+ samsung,mipi-enabled = <1>;
+ samsung,dp-enabled;
+ samsung,dual-lcd-enabled;
+
+ samsung,logo-on = <1>;
+ samsung,resolution = <0>;
+ samsung,rgb-mode = <0>;
+ };
+
+ mipidsi@11c80000 {
+ compatible = "samsung,exynos-mipi-dsi";
+ reg = <0x11c80000 0x5c>;
+
+ samsung,dsim-config-e-interface = <1>;
+ samsung,dsim-config-e-virtual-ch = <0>;
+ samsung,dsim-config-e-pixel-format = <7>;
+ samsung,dsim-config-e-burst-mode = <1>;
+ samsung,dsim-config-e-no-data-lane = <3>;
+ samsung,dsim-config-e-byte-clk = <0>;
+ samsung,dsim-config-hfp = <1>;
+
+ samsung,dsim-config-p = <3>;
+ samsung,dsim-config-m = <120>;
+ samsung,dsim-config-s = <1>;
+
+ samsung,dsim-config-pll-stable-time = <500>;
+ samsung,dsim-config-esc-clk = <20000000>;
+ samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+ samsung,dsim-config-bta-timeout = <0xff>;
+ samsung,dsim-config-rx-timeout = <0xffff>;
+
+ samsung,dsim-device-id = <0xffffffff>;
+ samsung,dsim-device-bus-id = <0>;
+
+ samsung,dsim-device-reverse-panel = <1>;
+ };
+
+ sdhci@12510000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ pwr-gpios = <&gpio 0x2004002 0>;
+ };
+
+ sdhci@12520000 {
+ status = "disabled";
+ };
+
+ sdhci@12530000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ cd-gpios = <&gpio 0x20C6004 0>;
+ };
+
+ sdhci@12540000 {
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 71bed4e..d9f0306 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -78,58 +78,7 @@
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-struct gpmc_cs {
- u32 config1; /* 0x00 */
- u32 config2; /* 0x04 */
- u32 config3; /* 0x08 */
- u32 config4; /* 0x0C */
- u32 config5; /* 0x10 */
- u32 config6; /* 0x14 */
- u32 config7; /* 0x18 */
- u32 nand_cmd; /* 0x1C */
- u32 nand_adr; /* 0x20 */
- u32 nand_dat; /* 0x24 */
- u8 res[8]; /* blow up to 0x30 byte */
-};
-
-struct bch_res_0_3 {
- u32 bch_result_x[4];
-};
-
-struct gpmc {
- u8 res1[0x10];
- u32 sysconfig; /* 0x10 */
- u8 res2[0x4];
- u32 irqstatus; /* 0x18 */
- u32 irqenable; /* 0x1C */
- u8 res3[0x20];
- u32 timeout_control; /* 0x40 */
- u8 res4[0xC];
- u32 config; /* 0x50 */
- u32 status; /* 0x54 */
- u8 res5[0x8]; /* 0x58 */
- struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
- u32 ecc_config; /* 0x1F4 */
- u32 ecc_control; /* 0x1F8 */
- u32 ecc_size_config; /* 0x1FC */
- u32 ecc1_result; /* 0x200 */
- u32 ecc2_result; /* 0x204 */
- u32 ecc3_result; /* 0x208 */
- u32 ecc4_result; /* 0x20C */
- u32 ecc5_result; /* 0x210 */
- u32 ecc6_result; /* 0x214 */
- u32 ecc7_result; /* 0x218 */
- u32 ecc8_result; /* 0x21C */
- u32 ecc9_result; /* 0x220 */
- u8 res7[12]; /* 0x224 */
- u32 testmomde_ctrl; /* 0x230 */
- u8 res8[12]; /* 0x234 */
- struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
-};
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
#ifndef CONFIG_AM43XX
/* Encapsulating core pll registers */
diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h
deleted file mode 100644
index 00ad1d0..0000000
--- a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_OMAP_GPMC_H
-#define __ASM_ARCH_OMAP_GPMC_H
-
-/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */
-#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
- .eccbytes = 32,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
- 28, 29, 30, 31, 32, 33},\
- .oobfree = {\
- {.offset = 34,\
- .length = 30 } } \
-}
-
-#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
- .eccbytes = 56,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
- 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
- 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
- 52, 53, 54, 55, 56, 57},\
- .oobfree = {\
- {.offset = 58,\
- .length = 6 } } \
-}
-
-#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
- .eccbytes = 104,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
- 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
- 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
- 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
- 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
- 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
- 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
- 100, 101, 102, 103, 104, 105},\
- .oobfree = {\
- {.offset = 106,\
- .length = 8 } } \
-}
-#endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 2e5c356..91ff2ad 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -10,6 +10,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
#include <asm/arch/cpu.h>
#define BOARD_REV_ID 0x0
diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h
index ff6142b..7121388 100644
--- a/arch/arm/include/asm/arch-at91/gpio.h
+++ b/arch/arm/include/asm/arch-at91/gpio.h
@@ -214,7 +214,7 @@ static inline unsigned pin_to_mask(unsigned pin)
/* The following macros are need for backward compatibility */
#define at91_set_GPIO_periph(x, y) \
- at91_set_gpio_periph((x - PIN_BASE) / 32,(x % 32), y)
+ at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_A_periph(x, y) \
at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_B_periph(x, y) \
diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h
index 68c5349..d8a87da 100644
--- a/arch/arm/include/asm/arch-at91/spl.h
+++ b/arch/arm/include/asm/arch-at91/spl.h
@@ -14,6 +14,10 @@ enum {
BOOT_DEVICE_MMC1,
BOOT_DEVICE_MMC2,
BOOT_DEVICE_MMC2_2,
+#elif CONFIG_SYS_USE_NANDFLASH
+ BOOT_DEVICE_NAND,
+#elif CONFIG_SYS_USE_SERIALFLASH
+ BOOT_DEVICE_SPI,
#endif
};
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 27b1844..98fe56e 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -15,7 +15,7 @@
#define __ASM_ARCH_HARDWARE_H
#include <config.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#define REG(addr) (*(volatile unsigned int *)(addr))
#define REG_P(addr) ((volatile unsigned int *)(addr))
diff --git a/arch/arm/include/asm/arch-exynos/board.h b/arch/arm/include/asm/arch-exynos/board.h
index 243fb12..1b1cd0d 100644
--- a/arch/arm/include/asm/arch-exynos/board.h
+++ b/arch/arm/include/asm/arch-exynos/board.h
@@ -14,4 +14,16 @@
*/
int exynos_init(void);
+/*
+ * Exynos board specific changes for
+ * board_early_init_f
+ */
+int exynos_early_init_f(void);
+
+/*
+ * Exynos board specific changes for
+ * board_power_init
+ */
+int exynos_power_init(void);
+
#endif /* EXYNOS_BOARD_H */
diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
index 40aca71..50e5c25 100644
--- a/arch/arm/include/asm/arch-exynos/mipi_dsim.h
+++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
@@ -12,6 +12,7 @@
#include <linux/list.h>
#include <linux/fb.h>
+#include <lcd.h>
#define PANEL_NAME_SIZE (32)
@@ -368,8 +369,12 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
*lcd_dev);
void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
+void exynos_init_dsim_platform_data(vidinfo_t *vid);
/* panel driver init based on mipi dsi interface */
void s6e8ax0_init(void);
+#ifdef CONFIG_OF_CONTROL
+extern int mipi_power(void);
+#endif
#endif /* _DSIM_H */
diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h
index 98d6530..0fb6461 100644
--- a/arch/arm/include/asm/arch-exynos/mmc.h
+++ b/arch/arm/include/asm/arch-exynos/mmc.h
@@ -53,6 +53,8 @@
#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
#define SDHCI_CTRL4_DRIVE_SHIFT (16)
+#define SDHCI_MAX_HOSTS 4
+
int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline int s5p_mmc_init(int index, int bus_width)
@@ -62,4 +64,9 @@ static inline int s5p_mmc_init(int index, int bus_width)
return s5p_sdhci_init(base, index, bus_width);
}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_mmc_init(const void *blob);
+#endif
+
#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
index 197703b..7a688e4 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -38,7 +38,7 @@
* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
*/
#ifndef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */
/* Kirkwood has 2k of Security SRAM, use it for SP */
diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h
index c0e3f20..42a52bc 100644
--- a/arch/arm/include/asm/arch-mb86r0x/hardware.h
+++ b/arch/arm/include/asm/arch-mb86r0x/hardware.h
@@ -9,7 +9,7 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#include <asm/arch/mb86r0x.h>
#endif
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 61ec8f2..4d06ef8 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -77,59 +77,7 @@ struct ctrl_id {
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct gpmc_cs {
- u32 config1; /* 0x00 */
- u32 config2; /* 0x04 */
- u32 config3; /* 0x08 */
- u32 config4; /* 0x0C */
- u32 config5; /* 0x10 */
- u32 config6; /* 0x14 */
- u32 config7; /* 0x18 */
- u32 nand_cmd; /* 0x1C */
- u32 nand_adr; /* 0x20 */
- u32 nand_dat; /* 0x24 */
- u8 res[8]; /* blow up to 0x30 byte */
-};
-
-struct bch_res_0_3 {
- u32 bch_result_x[4];
-};
-
-struct gpmc {
- u8 res1[0x10];
- u32 sysconfig; /* 0x10 */
- u8 res2[0x4];
- u32 irqstatus; /* 0x18 */
- u32 irqenable; /* 0x1C */
- u8 res3[0x20];
- u32 timeout_control; /* 0x40 */
- u8 res4[0xC];
- u32 config; /* 0x50 */
- u32 status; /* 0x54 */
- u8 res5[0x8]; /* 0x58 */
- struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
- u32 ecc_config; /* 0x1F4 */
- u32 ecc_control; /* 0x1F8 */
- u32 ecc_size_config; /* 0x1FC */
- u32 ecc1_result; /* 0x200 */
- u32 ecc2_result; /* 0x204 */
- u32 ecc3_result; /* 0x208 */
- u32 ecc4_result; /* 0x20C */
- u32 ecc5_result; /* 0x210 */
- u32 ecc6_result; /* 0x214 */
- u32 ecc7_result; /* 0x218 */
- u32 ecc8_result; /* 0x21C */
- u32 ecc9_result; /* 0x220 */
- u8 res7[0x1C]; /* fill up to 0x240 */
- struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
-#else /* __ASSEMBLY__ */
+#ifdef __ASSEMBLY__
#define GPMC_CONFIG1 0x00
#define GPMC_CONFIG2 0x04
#define GPMC_CONFIG3 0x08
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index bcc22c4..1804191 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -419,6 +419,16 @@ enum {
#define NET_GPMC_CONFIG6 0x00000FCF
#define NET_GPMC_CONFIG7 0x00000f6c
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1 0x00001000
+#define NET_LAN9221_GPMC_CONFIG2 0x00060700
+#define NET_LAN9221_GPMC_CONFIG3 0x00020201
+#define NET_LAN9221_GPMC_CONFIG4 0x06000700
+#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
+#define NET_LAN9221_GPMC_CONFIG6 0x87030000
+#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
+
+
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */
diff --git a/arch/arm/include/asm/arch-omap3/omap_gpmc.h b/arch/arm/include/asm/arch-omap3/omap_gpmc.h
deleted file mode 100644
index bf23219..0000000
--- a/arch/arm/include/asm/arch-omap3/omap_gpmc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_OMAP_GPMC_H
-#define __ASM_ARCH_OMAP_GPMC_H
-
-/*
- * These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library.
- * The OOB layout was first defined by linx kernel in commit
- * 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause
- * we want to be compatible.
- */
-#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
- .eccbytes = 56,\
- .eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\
- 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\
- 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\
- 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\
- .oobfree = {\
- {.offset = 2,\
- .length = 10 } } \
-}
-
-/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
-#define NET_LAN9221_GPMC_CONFIG1 0x00001000
-#define NET_LAN9221_GPMC_CONFIG2 0x00060700
-#define NET_LAN9221_GPMC_CONFIG3 0x00020201
-#define NET_LAN9221_GPMC_CONFIG4 0x06000700
-#define NET_LAN9221_GPMC_CONFIG5 0x0006090A
-#define NET_LAN9221_GPMC_CONFIG6 0x87030000
-#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
-
-#endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 43b54f7..44fa66f 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -7,6 +7,7 @@
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
typedef struct {
u32 mtype;
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 545d9d9..c21fb54 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -14,51 +14,6 @@
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-struct gpmc_cs {
- u32 config1; /* 0x00 */
- u32 config2; /* 0x04 */
- u32 config3; /* 0x08 */
- u32 config4; /* 0x0C */
- u32 config5; /* 0x10 */
- u32 config6; /* 0x14 */
- u32 config7; /* 0x18 */
- u32 nand_cmd; /* 0x1C */
- u32 nand_adr; /* 0x20 */
- u32 nand_dat; /* 0x24 */
- u8 res[8]; /* blow up to 0x30 byte */
-};
-
-struct gpmc {
- u8 res1[0x10];
- u32 sysconfig; /* 0x10 */
- u8 res2[0x4];
- u32 irqstatus; /* 0x18 */
- u32 irqenable; /* 0x1C */
- u8 res3[0x20];
- u32 timeout_control; /* 0x40 */
- u8 res4[0xC];
- u32 config; /* 0x50 */
- u32 status; /* 0x54 */
- u8 res5[0x8]; /* 0x58 */
- struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
- u32 ecc_config; /* 0x1F4 */
- u32 ecc_control; /* 0x1F8 */
- u32 ecc_size_config; /* 0x1FC */
- u32 ecc1_result; /* 0x200 */
- u32 ecc2_result; /* 0x204 */
- u32 ecc3_result; /* 0x208 */
- u32 ecc4_result; /* 0x20C */
- u32 ecc5_result; /* 0x210 */
- u32 ecc6_result; /* 0x214 */
- u32 ecc7_result; /* 0x218 */
- u32 ecc8_result; /* 0x21C */
- u32 ecc9_result; /* 0x220 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
struct gptimer {
u32 tidr; /* 0x00 r */
u8 res[0xc];
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index fc94725..b338a15 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -12,6 +12,7 @@
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
#include <asm/arch/mux_omap4.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index fb5a568..5f1d745 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -16,51 +16,6 @@
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-struct gpmc_cs {
- u32 config1; /* 0x00 */
- u32 config2; /* 0x04 */
- u32 config3; /* 0x08 */
- u32 config4; /* 0x0C */
- u32 config5; /* 0x10 */
- u32 config6; /* 0x14 */
- u32 config7; /* 0x18 */
- u32 nand_cmd; /* 0x1C */
- u32 nand_adr; /* 0x20 */
- u32 nand_dat; /* 0x24 */
- u8 res[8]; /* blow up to 0x30 byte */
-};
-
-struct gpmc {
- u8 res1[0x10];
- u32 sysconfig; /* 0x10 */
- u8 res2[0x4];
- u32 irqstatus; /* 0x18 */
- u32 irqenable; /* 0x1C */
- u8 res3[0x20];
- u32 timeout_control; /* 0x40 */
- u8 res4[0xC];
- u32 config; /* 0x50 */
- u32 status; /* 0x54 */
- u8 res5[0x8]; /* 0x58 */
- struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
- u32 ecc_config; /* 0x1F4 */
- u32 ecc_control; /* 0x1F8 */
- u32 ecc_size_config; /* 0x1FC */
- u32 ecc1_result; /* 0x200 */
- u32 ecc2_result; /* 0x204 */
- u32 ecc3_result; /* 0x208 */
- u32 ecc4_result; /* 0x20C */
- u32 ecc5_result; /* 0x210 */
- u32 ecc6_result; /* 0x214 */
- u32 ecc7_result; /* 0x218 */
- u32 ecc8_result; /* 0x21C */
- u32 ecc9_result; /* 0x220 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
-
struct gptimer {
u32 tidr; /* 0x00 r */
u8 res1[0xc];
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 43011a4..9e007c8 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -12,6 +12,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index 4c3264b..1dd3154 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -298,14 +298,25 @@ struct pmc_ctlr {
#define PMC_XOFS_SHIFT 1
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
+#if defined(CONFIG_TEGRA114)
#define TIMER_MULT_SHIFT 0
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 2
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
+#elif defined(CONFIG_TEGRA124)
+#define TIMER_MULT_SHIFT 0
+#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT 3
+#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT)
+#endif
+
#define MULT_1 0
#define MULT_2 1
#define MULT_4 2
#define MULT_8 3
+#if defined(CONFIG_TEGRA124)
+#define MULT_16 4
+#endif
#define AMAP_WRITE_SHIFT 20
#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 5fe19ae..d63af0e 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -34,7 +34,12 @@
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+ defined(CONFIG_TEGRA114)
#define NV_PA_CSITE_BASE 0x70040000
+#else
+#define NV_PA_CSITE_BASE 0x70800000
+#endif
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
index 5d426b5..705ca57 100644
--- a/arch/arm/include/asm/arch-tegra114/tegra.h
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -17,6 +17,8 @@
#ifndef _TEGRA114_H_
#define _TEGRA114_H_
+#define CONFIG_TEGRA114
+
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h
index db3d837..86ebd19 100644
--- a/arch/arm/include/asm/arch-tegra124/tegra.h
+++ b/arch/arm/include/asm/arch-tegra124/tegra.h
@@ -8,6 +8,8 @@
#ifndef _TEGRA124_H_
#define _TEGRA124_H_
+#define CONFIG_TEGRA124
+
#define NV_PA_SDRAM_BASE 0x80000000
#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
index 18856ac..6a4b40e 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -8,6 +8,8 @@
#ifndef _TEGRA20_H_
#define _TEGRA20_H_
+#define CONFIG_TEGRA20
+
#define NV_PA_SDRAM_BASE 0x00000000
#include <asm/arch-tegra/tegra.h>
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
index c02c5d8..4ad8b1c 100644
--- a/arch/arm/include/asm/arch-tegra30/tegra.h
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -17,6 +17,8 @@
#ifndef _TEGRA30_H_
#define _TEGRA30_H_
+#define CONFIG_TEGRA30
+
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
#include <asm/arch-tegra/tegra.h>
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
index aed6c46..2a7ca4e 100644
--- a/arch/arm/include/asm/arch-tnetv107x/hardware.h
+++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h
@@ -9,7 +9,7 @@
#ifndef __ASSEMBLY__
-#include <asm/sizes.h>
+#include <linux/sizes.h>
#define ASYNC_EMIF_NUM_CS 4
#define ASYNC_EMIF_MODE_NOR 0
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 0a2ba05..a68e1b3 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -19,5 +19,6 @@ extern void zynq_ddrc_init(void);
/* Driver extern functions */
extern int zynq_sdhci_init(u32 regbase);
+extern int zynq_sdhci_of_init(const void *blob);
#endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/include/asm/omap_elm.h b/arch/arm/include/asm/omap_elm.h
deleted file mode 100644
index 45454ea..0000000
--- a/arch/arm/include/asm/omap_elm.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
- * Mansoor Ahamed <mansoor.ahamed@ti.com>
- *
- * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_ELM_H
-#define __ASM_ARCH_ELM_H
-/*
- * ELM Module Registers
- */
-
-/* ELM registers bit fields */
-#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2)
-#define ELM_SYSCONFIG_SOFTRESET (0x2)
-#define ELM_SYSSTATUS_RESETDONE_MASK (0x1)
-#define ELM_SYSSTATUS_RESETDONE (0x1)
-#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3)
-#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000)
-#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16)
-#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000)
-#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100)
-#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F)
-
-#ifndef __ASSEMBLY__
-
-enum bch_level {
- BCH_4_BIT = 0,
- BCH_8_BIT,
- BCH_16_BIT
-};
-
-
-/* BCH syndrome registers */
-struct syndrome {
- u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */
- u8 res1[36]; /* 0x41c */
-};
-
-/* BCH error status & location register */
-struct location {
- u32 location_status; /* 0x800 */
- u8 res1[124]; /* 0x804 */
- u32 error_location_x[16]; /* 0x880.... */
- u8 res2[64]; /* 0x8c0 */
-};
-
-/* BCH ELM register map - do not try to allocate memmory for this structure.
- * We have used plenty of reserved variables to fill the slots in the ELM
- * register memory map.
- * Directly initialize the struct pointer to ELM base address.
- */
-struct elm {
- u32 rev; /* 0x000 */
- u8 res1[12]; /* 0x004 */
- u32 sysconfig; /* 0x010 */
- u32 sysstatus; /* 0x014 */
- u32 irqstatus; /* 0x018 */
- u32 irqenable; /* 0x01c */
- u32 location_config; /* 0x020 */
- u8 res2[92]; /* 0x024 */
- u32 page_ctrl; /* 0x080 */
- u8 res3[892]; /* 0x084 */
- struct syndrome syndrome_fragments[8]; /* 0x400 */
- u8 res4[512]; /* 0x600 */
- struct location error_location[8]; /* 0x800 */
-};
-
-int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
- u32 *error_locations);
-int elm_config(enum bch_level level);
-void elm_reset(void);
-void elm_init(void);
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_ELM_H */
diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h
deleted file mode 100644
index d4143ec..0000000
--- a/arch/arm/include/asm/omap_gpmc.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
- * Rohit Choraria <rohitkc@ti.com>
- *
- * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_OMAP_GPMC_H
-#define __ASM_OMAP_GPMC_H
-
-#include <asm/arch/omap_gpmc.h>
-
-#define GPMC_BUF_EMPTY 0
-#define GPMC_BUF_FULL 1
-
-#define ECCCLEAR (0x1 << 8)
-#define ECCRESULTREG1 (0x1 << 0)
-#define ECCSIZE512BYTE 0xFF
-#define ECCSIZE1 (ECCSIZE512BYTE << 22)
-#define ECCSIZE0 (ECCSIZE512BYTE << 12)
-#define ECCSIZE0SEL (0x000 << 0)
-
-/* Generic ECC Layouts */
-/* Large Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 12,\
- .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
- 9, 10, 11, 12},\
- .oobfree = {\
- {.offset = 13,\
- .length = 51 } } \
-}
-#endif
-
-/* Large Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 12,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13},\
- .oobfree = {\
- {.offset = 14,\
- .length = 50 } } \
-}
-#endif
-
-/* Small Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 3,\
- .eccpos = {1, 2, 3},\
- .oobfree = {\
- {.offset = 4,\
- .length = 12 } } \
-}
-#endif
-
-/* Small Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 3,\
- .eccpos = {2, 3, 4},\
- .oobfree = {\
- {.offset = 5,\
- .length = 11 } } \
-}
-#endif
-
-enum omap_ecc {
- /* 1-bit ECC calculation by Software, Error detection by Software */
- OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
- /* 1-bit ECC calculation by GPMC, Error detection by Software */
- /* ECC layout compatible to legacy ROMCODE. */
- OMAP_ECC_HAM1_CODE_HW,
- /* 4-bit ECC calculation by GPMC, Error detection by Software */
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
- /* 4-bit ECC calculation by GPMC, Error detection by ELM */
- OMAP_ECC_BCH4_CODE_HW,
- /* 8-bit ECC calculation by GPMC, Error detection by Software */
- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
- /* 8-bit ECC calculation by GPMC, Error detection by ELM */
- OMAP_ECC_BCH8_CODE_HW,
-};
-
-#endif /* __ASM_OMAP_GPMC_H */
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
deleted file mode 100644
index 28cf5ea..0000000
--- a/arch/arm/include/asm/sizes.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* Size defintions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_1K 0x00000400
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_32K 0x00008000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_31M 0x01F00000
-#define SZ_32M 0x02000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif
-
-/* END */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 45febcf..9fc81cd 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,17 +5,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Build private libgcc only when asked for
-ifdef USE_PRIVATE_LIBGCC
-lib-y += _ashldi3.o
-lib-y += _ashrdi3.o
-lib-y += _divsi3.o
-lib-y += _lshrdi3.o
-lib-y += _modsi3.o
-lib-y += _udivsi3.o
-lib-y += _umodsi3.o
-lib-y += div0.o
-endif
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
+ _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o
ifdef CONFIG_ARM64
obj-y += crt0_64.o
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index e9a7708..92e85c4 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -33,6 +33,7 @@
#include <nand.h>
#include <onenand_uboot.h>
#include <mmc.h>
+#include <scsi.h>
#include <libfdt.h>
#include <fdtdec.h>
#include <post.h>
@@ -593,6 +594,11 @@ void board_init_r(gd_t *id, ulong dest_addr)
mmc_initialize(gd->bd);
#endif
+#ifdef CONFIG_CMD_SCSI
+ puts("SCSI: ");
+ scsi_init();
+#endif
+
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();