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authorWolfgang Denk <wd@denx.de>2011-12-12 07:58:58 +0100
committerWolfgang Denk <wd@denx.de>2011-12-12 07:58:58 +0100
commitb2eb7d9bc6032e16b7dd898f7c0ea654f63b61db (patch)
treeb8b649483183d93dedfcb5512d0b9720aa91644f /arch/arm
parent4f1a2cd1637027f31de7796aedb1fa5fc0ec0f97 (diff)
parentd98d8bc1c913a5a1aea6b17365f90c430d1fc95a (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-usb
* 'master' of git://git.denx.de/u-boot-usb: USB: efikamx: Enable USB on EfikaMX and EfikaSB USB: Add generic ULPI layer and a viewport USB: EHCI: Allow EHCI post-powerup configuration in board files USB: mx51evk: add end enable USB host support on port 1 USB: mx53loco: add end enable USB host support on port 1 USB: MX5: Add MX5 usb post-init callback USB: MX5: Abstract out mx51 USB pixmux configuration USB: MX5: add generic USB EHCI support for mx51 and mx53 USB: MX5: add helper functions to enable USB clocks usb:gadget:s5p Enable the USB Gadget framework at GONI usb:gadget:s5p USB Device Controller (UDC) implementation ehci: speed up initialization usb: add help for missing start subcommand cosmetic: remove excess whitespace from usb command help usb: align usb_endpoint_descriptor to 16-bit boundary usbtty: init endpoints prior to startup events pxa: convert pxa27x_udc to use read and write functions pxa: activate the first usb host port on pxa27x by default pxa: fix usb host register mismatch ehci-fsl: correct size of ehci caplength USB: Add usb_event_poll() to get keyboards working with EHCI USB: gadaget: add Marvell controller support USB: Fix complaints about strict aliasing in OHCI-HCD USB: Drop dead code from usb_kbd.c USB: Rework usb_kbd.c USB: Add functionality to poll the USB keyboard via control EP
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/mx5/clock.c72
-rw-r--r--arch/arm/cpu/pxa/usb.c6
-rw-r--r--arch/arm/include/asm/arch-mx5/clock.h5
-rw-r--r--arch/arm/include/asm/arch-mx5/crm_regs.h3
-rw-r--r--arch/arm/include/asm/arch-pxa/pxa-regs.h10
-rw-r--r--arch/arm/include/asm/arch-s5pc1xx/cpu.h4
6 files changed, 93 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 933ce05..e92f106 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -50,6 +50,78 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+void set_usboh3_clk(void)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->cscmr1) &
+ ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
+ reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
+ writel(reg, &mxc_ccm->cscmr1);
+
+ reg = readl(&mxc_ccm->cscdr1);
+ reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
+ reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
+ reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
+
+ writel(reg, &mxc_ccm->cscdr1);
+}
+
+void enable_usboh3_clk(unsigned char enable)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->CCGR2);
+ if (enable)
+ reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
+ else
+ reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
+ writel(reg, &mxc_ccm->CCGR2);
+}
+
+void set_usb_phy1_clk(void)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+ writel(reg, &mxc_ccm->cscmr1);
+}
+
+void enable_usb_phy1_clk(unsigned char enable)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->CCGR4);
+ if (enable)
+ reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
+ else
+ reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
+ writel(reg, &mxc_ccm->CCGR4);
+}
+
+void set_usb_phy2_clk(void)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+ writel(reg, &mxc_ccm->cscmr1);
+}
+
+void enable_usb_phy2_clk(unsigned char enable)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->CCGR4);
+ if (enable)
+ reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
+ else
+ reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
+ writel(reg, &mxc_ccm->CCGR4);
+}
+
/*
* Calculate the frequency of PLLn.
*/
diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c
index 83022e2..307fc6c 100644
--- a/arch/arm/cpu/pxa/usb.c
+++ b/arch/arm/cpu/pxa/usb.c
@@ -55,7 +55,7 @@ int usb_cpu_init(void)
while (readl(UHCHR) & UHCHR_FSBIR)
udelay(1);
-#if defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_CPU_PXA27X)
@@ -72,10 +72,10 @@ int usb_cpu_stop(void)
udelay(11);
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS);
+ writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
udelay(10);
-#if defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_CPU_PXA27X)
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 1f8a537..ea972a3 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -40,4 +40,9 @@ u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
+void set_usb_phy2_clk(void);
+void enable_usb_phy2_clk(unsigned char enable);
+void set_usboh3_clk(void);
+void enable_usboh3_clk(unsigned char enable);
+
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index fcc0e36..bdeafbc 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -195,7 +195,10 @@ struct mxc_ccm_reg {
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
+#define MXC_CCM_CCGR4_CG5_OFFSET 10
+#define MXC_CCM_CCGR4_CG6_OFFSET 12
#define MXC_CCM_CCGR5_CG5_OFFSET 10
+#define MXC_CCM_CCGR2_CG14_OFFSET 28
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index 8527c68..b81b42c 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -645,7 +645,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */
-#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
+#define UDCCSN(x) (0x40600100 + ((x) << 2))
#define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
@@ -693,7 +693,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCSR_PC (1 << 1) /* Packet Complete */
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
-#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
+#define UDCBCN(x) (0x40600200 + ((x) << 2))
#define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */
#define UDCBCRA 0x40600204 /* Byte Count Register - EPA */
#define UDCBCRB 0x40600208 /* Byte Count Register - EPB */
@@ -719,7 +719,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCBCRW 0x40600258 /* Byte Count Register - EPW */
#define UDCBCRX 0x4060025C /* Byte Count Register - EPX */
-#define UDCDN(x) __REG2(0x40600300, (x)<<2)
+#define UDCDN(x) (0x40600300 + ((x) << 2))
#define UDCDR0 0x40600300 /* Data Register - EP0 */
#define UDCDRA 0x40600304 /* Data Register - EPA */
#define UDCDRB 0x40600308 /* Data Register - EPB */
@@ -745,7 +745,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCDRW 0x40600358 /* Data Register - EPW */
#define UDCDRX 0x4060035C /* Data Register - EPX */
-#define UDCCN(x) __REG2(0x40600400, (x)<<2)
+#define UDCCN(x) (0x40600400 + ((x) << 2))
#define UDCCRA 0x40600404 /* Configuration register EPA */
#define UDCCRB 0x40600408 /* Configuration register EPB */
#define UDCCRC 0x4060040C /* Configuration register EPC */
@@ -835,6 +835,8 @@ typedef void (*ExcpHndlr) (void) ;
#define UHCHIE 0x4C000068
#define UHCHIT 0x4C00006C
+#define UHCCOMS_HCR (1<<0)
+
#define UHCHR_FSBIR (1<<0)
#define UHCHR_FHR (1<<1)
#define UHCHR_CGR (1<<2)
diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
index e74959f..e699fc4 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
@@ -55,6 +55,10 @@
#define S5PC110_VIC1_BASE 0xF2100000
#define S5PC110_VIC2_BASE 0xF2200000
#define S5PC110_VIC3_BASE 0xF2300000
+#define S5PC110_OTG_BASE 0xEC000000
+#define S5PC110_PHY_BASE 0xEC100000
+#define S5PC110_USB_PHY_CONTROL 0xE010E80C
+
#ifndef __ASSEMBLY__
#include <asm/io.h>