From 1c0a14ebb7beb5d1d8f9893aea95e42eded95c1c Mon Sep 17 00:00:00 2001 From: Stefan Herbrechtsmeier Date: Mon, 17 Oct 2011 17:22:46 +0200 Subject: pxa: fix usb host register mismatch Signed-off-by: Stefan Herbrechtsmeier CC: Marek Vasut CC: Remy Bohmer --- arch/arm/cpu/pxa/usb.c | 2 +- arch/arm/include/asm/arch-pxa/pxa-regs.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c index 83022e2..e95e0df 100644 --- a/arch/arm/cpu/pxa/usb.c +++ b/arch/arm/cpu/pxa/usb.c @@ -72,7 +72,7 @@ int usb_cpu_stop(void) udelay(11); writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS); + writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS); udelay(10); #if defined(CONFIG_CPU_MONAHANS) diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index 8527c68..0c3cd6d 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -835,6 +835,8 @@ typedef void (*ExcpHndlr) (void) ; #define UHCHIE 0x4C000068 #define UHCHIT 0x4C00006C +#define UHCCOMS_HCR (1<<0) + #define UHCHR_FSBIR (1<<0) #define UHCHR_FHR (1<<1) #define UHCHR_CGR (1<<2) -- cgit v1.1 From 66a181864d910afd7188ddbd747c70da96f7c505 Mon Sep 17 00:00:00 2001 From: Stefan Herbrechtsmeier Date: Mon, 17 Oct 2011 17:22:47 +0200 Subject: pxa: activate the first usb host port on pxa27x by default The pxa27x has 3 usb host ports. Activate all by default. Signed-off-by: Stefan Herbrechtsmeier CC: Marek Vasut CC: Remy Bohmer --- arch/arm/cpu/pxa/usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c index e95e0df..307fc6c 100644 --- a/arch/arm/cpu/pxa/usb.c +++ b/arch/arm/cpu/pxa/usb.c @@ -55,7 +55,7 @@ int usb_cpu_init(void) while (readl(UHCHR) & UHCHR_FSBIR) udelay(1); -#if defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_CPU_PXA27X) @@ -75,7 +75,7 @@ int usb_cpu_stop(void) writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS); udelay(10); -#if defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_CPU_PXA27X) -- cgit v1.1 From bdbcdc897f9e854ca8a4701418dec048ef376431 Mon Sep 17 00:00:00 2001 From: Stefan Herbrechtsmeier Date: Mon, 17 Oct 2011 17:22:48 +0200 Subject: pxa: convert pxa27x_udc to use read and write functions Signed-off-by: Stefan Herbrechtsmeier CC: Marek Vasut CC: Remy Bohmer --- arch/arm/include/asm/arch-pxa/pxa-regs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index 0c3cd6d..b81b42c 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -645,7 +645,7 @@ typedef void (*ExcpHndlr) (void) ; #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */ #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */ -#define UDCCSN(x) __REG2(0x40600100, (x) << 2) +#define UDCCSN(x) (0x40600100 + ((x) << 2)) #define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */ #define UDCCSR0_SA (1 << 7) /* Setup Active */ @@ -693,7 +693,7 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSR_PC (1 << 1) /* Packet Complete */ #define UDCCSR_FS (1 << 0) /* FIFO needs service */ -#define UDCBCN(x) __REG2(0x40600200, (x)<<2) +#define UDCBCN(x) (0x40600200 + ((x) << 2)) #define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */ #define UDCBCRA 0x40600204 /* Byte Count Register - EPA */ #define UDCBCRB 0x40600208 /* Byte Count Register - EPB */ @@ -719,7 +719,7 @@ typedef void (*ExcpHndlr) (void) ; #define UDCBCRW 0x40600258 /* Byte Count Register - EPW */ #define UDCBCRX 0x4060025C /* Byte Count Register - EPX */ -#define UDCDN(x) __REG2(0x40600300, (x)<<2) +#define UDCDN(x) (0x40600300 + ((x) << 2)) #define UDCDR0 0x40600300 /* Data Register - EP0 */ #define UDCDRA 0x40600304 /* Data Register - EPA */ #define UDCDRB 0x40600308 /* Data Register - EPB */ @@ -745,7 +745,7 @@ typedef void (*ExcpHndlr) (void) ; #define UDCDRW 0x40600358 /* Data Register - EPW */ #define UDCDRX 0x4060035C /* Data Register - EPX */ -#define UDCCN(x) __REG2(0x40600400, (x)<<2) +#define UDCCN(x) (0x40600400 + ((x) << 2)) #define UDCCRA 0x40600404 /* Configuration register EPA */ #define UDCCRB 0x40600408 /* Configuration register EPB */ #define UDCCRC 0x4060040C /* Configuration register EPC */ -- cgit v1.1 From a954da2902e2e0fc54942691d6e0d64a7a1b3c3a Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 27 Oct 2011 10:36:47 +0200 Subject: usb:gadget:s5p Enable the USB Gadget framework at GONI This commit enables support for USB Gadgets on the GONI reference target. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Cc: Minkyu Kang Cc: Remy Bohmer --- arch/arm/include/asm/arch-s5pc1xx/cpu.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h index e74959f..e699fc4 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h @@ -55,6 +55,10 @@ #define S5PC110_VIC1_BASE 0xF2100000 #define S5PC110_VIC2_BASE 0xF2200000 #define S5PC110_VIC3_BASE 0xF2300000 +#define S5PC110_OTG_BASE 0xEC000000 +#define S5PC110_PHY_BASE 0xEC100000 +#define S5PC110_USB_PHY_CONTROL 0xE010E80C + #ifndef __ASSEMBLY__ #include -- cgit v1.1 From 5d2947a3fc8d130cfa39fccdefb87082abbf0e9b Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Fri, 11 Nov 2011 14:03:34 +0100 Subject: USB: MX5: add helper functions to enable USB clocks Signed-off-by: Wolfgang Grandegger Cc: Stefano Babic Cc: Remy Bohmer Cc: Wolfgang Grandegger Cc: Jason Liu V2: Fix spacing in crm_regs.h --- arch/arm/cpu/armv7/mx5/clock.c | 72 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx5/clock.h | 5 +++ arch/arm/include/asm/arch-mx5/crm_regs.h | 3 ++ 3 files changed, 80 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 933ce05..e92f106 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -50,6 +50,78 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; +void set_usboh3_clk(void) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->cscmr1) & + ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; + reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; + writel(reg, &mxc_ccm->cscmr1); + + reg = readl(&mxc_ccm->cscdr1); + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; + reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; + reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; + + writel(reg, &mxc_ccm->cscdr1); +} + +void enable_usboh3_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->CCGR2); + if (enable) + reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET); + writel(reg, &mxc_ccm->CCGR2); +} + +void set_usb_phy1_clk(void) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->cscmr1); + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + writel(reg, &mxc_ccm->cscmr1); +} + +void enable_usb_phy1_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->CCGR4); + if (enable) + reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET); + writel(reg, &mxc_ccm->CCGR4); +} + +void set_usb_phy2_clk(void) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->cscmr1); + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + writel(reg, &mxc_ccm->cscmr1); +} + +void enable_usb_phy2_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->CCGR4); + if (enable) + reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET); + writel(reg, &mxc_ccm->CCGR4); +} + /* * Calculate the frequency of PLLn. */ diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 1f8a537..ea972a3 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -40,4 +40,9 @@ u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); +void set_usb_phy2_clk(void); +void enable_usb_phy2_clk(unsigned char enable); +void set_usboh3_clk(void); +void enable_usboh3_clk(unsigned char enable); + #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index fcc0e36..bdeafbc 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -195,7 +195,10 @@ struct mxc_ccm_reg { /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 +#define MXC_CCM_CCGR4_CG5_OFFSET 10 +#define MXC_CCM_CCGR4_CG6_OFFSET 12 #define MXC_CCM_CCGR5_CG5_OFFSET 10 +#define MXC_CCM_CCGR2_CG14_OFFSET 28 /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) -- cgit v1.1