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authorhuang lin <hl@rock-chips.com>2015-11-17 14:20:27 +0800
committerSimon Glass <sjg@chromium.org>2015-12-01 08:07:22 -0700
commitbe1d5e0388d2e506d875d4b984485526bdf3197f (patch)
tree8118089e14f8848081646826253e8ada3d9379ef /arch/arm/thumb1
parent53c45f0ca27cbf6acd840e87beaa1ba1be74399b (diff)
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rockchip: rk3036: Add core Soc start-up code
rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
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