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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-07-21 14:04:22 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-07-23 23:42:22 +0900 |
commit | 3365b4eb5543ae26579321da34cca42e38ac130f (patch) | |
tree | 3da8e615f2f020eda20f50cef1b79b83c36e4bd3 /arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | |
parent | ad6670ee12a1783aeb54881fa5bb2e5582ba2dbc (diff) | |
download | u-boot-imx-3365b4eb5543ae26579321da34cca42e38ac130f.zip u-boot-imx-3365b4eb5543ae26579321da34cca42e38ac130f.tar.gz u-boot-imx-3365b4eb5543ae26579321da34cca42e38ac130f.tar.bz2 |
ARM: UniPhier: add PH1-sLD3 SoC support
The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/ph1-sld3/sbc_init.c')
-rw-r--r-- | arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c new file mode 100644 index 0000000..d66f89e --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + /* only address/data multiplex mode is supported */ + + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * + * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank + * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x00000000-0x01ffffff: mask ROM + * 0x02000000-0x03efffff: memory bank (31MB) + * 0x03f00000-0x03ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } + + sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */ +} |