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| author | Stefano Babic <sbabic@denx.de> | 2015-03-05 16:05:10 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-03-05 16:05:10 +0100 |
| commit | 9b5b60a05cb8bba2d135439419b2030764e359bd (patch) | |
| tree | 15e249ac39e9c547668327218e63a0faf54a3283 /arch/arm/mach-uniphier/ph1-ld4/sbc_init.c | |
| parent | 32df39c741788e8637cffe6633d73594b26d70fb (diff) | |
| parent | 7ae8350f67eea861280a4cbd2d067777a0e87153 (diff) | |
| download | u-boot-imx-9b5b60a05cb8bba2d135439419b2030764e359bd.zip u-boot-imx-9b5b60a05cb8bba2d135439419b2030764e359bd.tar.gz u-boot-imx-9b5b60a05cb8bba2d135439419b2030764e359bd.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/arm/mach-uniphier/ph1-ld4/sbc_init.c')
| -rw-r--r-- | arch/arm/mach-uniphier/ph1-ld4/sbc_init.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c new file mode 100644 index 0000000..00f8461 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/sbc-regs.h> +#include <mach/sg-regs.h> + +void sbc_init(void) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * + * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank + * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x00000000-0x01ffffff: mask ROM + * 0x02000000-0x03efffff: memory bank (31MB) + * 0x03f00000-0x03ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } +} |