diff options
author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-03-23 00:07:32 +0900 |
---|---|---|
committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-03-24 00:15:58 +0900 |
commit | a509161a21ef7584d614dc1530a2756dcfb217e0 (patch) | |
tree | 01a59554b7e9281d97896ccb0e4a766bbd88d8c6 /arch/arm/mach-uniphier/late_lowlevel_init.S | |
parent | 62118b7b0183d29755a101a6a5b88dee11c5f94b (diff) | |
download | u-boot-imx-a509161a21ef7584d614dc1530a2756dcfb217e0.zip u-boot-imx-a509161a21ef7584d614dc1530a2756dcfb217e0.tar.gz u-boot-imx-a509161a21ef7584d614dc1530a2756dcfb217e0.tar.bz2 |
ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot proper
The L2 cache is used as a temporary SRAM on SPL.
Now the secondary CPUs store the necessary code for jumping to
Linux on their L1 I-caches. So, the L2 cache can be disabled
much earlier, at the very entry of U-Boot proper (lowlevel_init).
This makes the boot sequence clearer.
Also, as the L1 cache has been disabled by the start.S,
enable_caches() does not need to do it again.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/late_lowlevel_init.S')
-rw-r--r-- | arch/arm/mach-uniphier/late_lowlevel_init.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S index 22be2a2..1363364 100644 --- a/arch/arm/mach-uniphier/late_lowlevel_init.S +++ b/arch/arm/mach-uniphier/late_lowlevel_init.S @@ -6,7 +6,12 @@ */ #include <linux/linkage.h> +#include <mach/ssc-regs.h> ENTRY(lowlevel_init) + ldr r1, = SSCC + ldr r0, [r1] + bic r0, r0, #SSCC_ON @ L2 disable + str r0, [r1] mov pc, lr ENDPROC(lowlevel_init) |