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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-02-05 10:52:12 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-02-23 08:37:56 +0900 |
commit | 04cd4e7215d30431b736ef89c16d241c50a90c37 (patch) | |
tree | b46fbd5ce22dac559d413253d5d60646f12d6dde /arch/arm/mach-uniphier/dram_init.c | |
parent | cf3175bcd8b21a87276016aceb9d7992a2151fca (diff) | |
download | u-boot-imx-04cd4e7215d30431b736ef89c16d241c50a90c37.zip u-boot-imx-04cd4e7215d30431b736ef89c16d241c50a90c37.tar.gz u-boot-imx-04cd4e7215d30431b736ef89c16d241c50a90c37.tar.bz2 |
ARM: uniphier: remove DRAM base address from board parameters
The base address of each DRAM channel can be calculated from other
parameters, so does not need hard-coding. What we need is the size
of each DRAM channel and DRAM_SPARSE flag to decide the start address
of DRAM channel 1.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/dram_init.c')
-rw-r--r-- | arch/arm/mach-uniphier/dram_init.c | 53 |
1 files changed, 30 insertions, 23 deletions
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index b9b0cd6..d9f6c16 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -11,10 +11,12 @@ #include <linux/errno.h> #include <linux/sizes.h> -#include "init.h" #include "sg-regs.h" #include "soc-info.h" +#define pr_warn(fmt, args...) printf(fmt, ##args) +#define pr_err(fmt, args...) printf(fmt, ##args) + DECLARE_GLOBAL_DATA_PTR; struct uniphier_memif_data { @@ -76,7 +78,12 @@ static const struct uniphier_memif_data uniphier_memif_data[] = { }; UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data) -static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) +struct uniphier_dram_map { + unsigned long base; + unsigned long size; +}; + +static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) { const struct uniphier_memif_data *data; unsigned long size; @@ -91,7 +98,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) val = readl(SG_MEMCONF); /* set up ch0 */ - dram_ch[0].base = CONFIG_SYS_SDRAM_BASE; + dram_map[0].base = CONFIG_SYS_SDRAM_BASE; switch (val & SG_MEMCONF_CH0_SZ_MASK) { case SG_MEMCONF_CH0_SZ_64M: @@ -117,20 +124,20 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2) size *= 2; - dram_ch[0].size = size; + dram_map[0].size = size; /* set up ch1 */ - dram_ch[1].base = dram_ch[0].base + size; + dram_map[1].base = dram_map[0].base + size; if (val & SG_MEMCONF_SPARSEMEM) { - if (dram_ch[1].base > data->sparse_ch1_base) { + if (dram_map[1].base > data->sparse_ch1_base) { pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n"); pr_warn("Only ch0 is available\n"); - dram_ch[1].base = 0; + dram_map[1].base = 0; return 0; } - dram_ch[1].base = data->sparse_ch1_base; + dram_map[1].base = data->sparse_ch1_base; } switch (val & SG_MEMCONF_CH1_SZ_MASK) { @@ -157,13 +164,13 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2) size *= 2; - dram_ch[1].size = size; + dram_map[1].size = size; if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE) return 0; /* set up ch2 */ - dram_ch[2].base = dram_ch[1].base + size; + dram_map[2].base = dram_map[1].base + size; switch (val & SG_MEMCONF_CH2_SZ_MASK) { case SG_MEMCONF_CH2_SZ_64M: @@ -189,25 +196,25 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2) size *= 2; - dram_ch[2].size = size; + dram_map[2].size = size; return 0; } int dram_init(void) { - struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {}; + struct uniphier_dram_map dram_map[3] = {}; int ret, i; gd->ram_size = 0; - ret = uniphier_memconf_decode(dram_ch); + ret = uniphier_memconf_decode(dram_map); if (ret) return ret; - for (i = 0; i < ARRAY_SIZE(dram_ch); i++) { + for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (!dram_ch[i].size) + if (!dram_map[i].size) break; /* @@ -215,11 +222,11 @@ int dram_init(void) * but it does not expect sparse memory. We use the first * contiguous chunk here. */ - if (i > 0 && - dram_ch[i - 1].base + dram_ch[i - 1].size < dram_ch[i].base) + if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size < + dram_map[i].base) break; - gd->ram_size += dram_ch[i].size; + gd->ram_size += dram_map[i].size; } return 0; @@ -227,17 +234,17 @@ int dram_init(void) void dram_init_banksize(void) { - struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {}; + struct uniphier_dram_map dram_map[3] = {}; int i; - uniphier_memconf_decode(dram_ch); + uniphier_memconf_decode(dram_map); - for (i = 0; i < ARRAY_SIZE(dram_ch); i++) { + for (i = 0; i < ARRAY_SIZE(dram_map); i++) { if (i >= ARRAY_SIZE(gd->bd->bi_dram)) break; - gd->bd->bi_dram[i].start = dram_ch[i].base; - gd->bd->bi_dram[i].size = dram_ch[i].size; + gd->bd->bi_dram[i].start = dram_map[i].base; + gd->bd->bi_dram[i].size = dram_map[i].size; } } |