diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-26 14:21:38 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-29 03:50:16 +0900 |
| commit | 00dd3f6ab068276f8baa409e9317fbf466187a34 (patch) | |
| tree | bdc2a6417b93553f6c641d77bc7e5fd7547364e8 /arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c | |
| parent | 94b756f3318b5dea3c1aefa670f43ae85d780144 (diff) | |
| download | u-boot-imx-00dd3f6ab068276f8baa409e9317fbf466187a34.zip u-boot-imx-00dd3f6ab068276f8baa409e9317fbf466187a34.tar.gz u-boot-imx-00dd3f6ab068276f8baa409e9317fbf466187a34.tar.bz2 | |
ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings
These settings were used only for the PH1-sLD3 and older SoCs. The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c')
0 files changed, 0 insertions, 0 deletions