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| author | Tom Rini <trini@konsulko.com> | 2016-09-18 12:12:04 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-09-18 14:05:30 -0400 |
| commit | 9a6535e05f17acf03e891266a650cb6029124743 (patch) | |
| tree | fec0cd46e0f050812deecf89b8bb349c8fdffd0e /arch/arm/mach-uniphier/clk/dpll-ld4.c | |
| parent | b58d3512442357cb023bce69f55c08b9fd21beaa (diff) | |
| parent | f9d7e17e844f9e94c39a8c95f73a4454097a6948 (diff) | |
| download | u-boot-imx-9a6535e05f17acf03e891266a650cb6029124743.zip u-boot-imx-9a6535e05f17acf03e891266a650cb6029124743.tar.gz u-boot-imx-9a6535e05f17acf03e891266a650cb6029124743.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
Diffstat (limited to 'arch/arm/mach-uniphier/clk/dpll-ld4.c')
| -rw-r--r-- | arch/arm/mach-uniphier/clk/dpll-ld4.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c new file mode 100644 index 0000000..a40b30d --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/err.h> +#include <linux/io.h> + +#include "../init.h" +#include "../sc-regs.h" + +#undef DPLL_SSC_RATE_1PER + +int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) +{ + unsigned int dram_freq = bd->dram_freq; + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT (DPLLCTRL.bit[29:20]) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x000f0000; + switch (dram_freq) { + case 1333: + tmp |= 0x000d0000; + break; + case 1600: + tmp |= 0x000c0000; + break; + default: + pr_err("Unsupported frequency"); + return -EINVAL; + } + +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~SC_DPLLCTRL_SSC_RATE; +#else + tmp |= SC_DPLLCTRL_SSC_RATE; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); + + /* Wait 500 usec until dpll gets stable */ + udelay(500); + + return 0; +} |