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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-03-18 16:41:43 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-03-24 01:42:13 +0900 |
| commit | ea65c98050f0f13f933119e1d073c8a138481ee4 (patch) | |
| tree | 47fd29a996ceb41bfb974dc09b02ae518d3412d6 /arch/arm/mach-uniphier/clk/clk-pro4.c | |
| parent | 013dcc7863b990f7bd0680e1ced320bf6a963e8f (diff) | |
| download | u-boot-imx-ea65c98050f0f13f933119e1d073c8a138481ee4.zip u-boot-imx-ea65c98050f0f13f933119e1d073c8a138481ee4.tar.gz u-boot-imx-ea65c98050f0f13f933119e1d073c8a138481ee4.tar.bz2 | |
ARM: uniphier: drop PH1- prefix from CONFIG options and file names
The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too
long. It would not hurt to drop "PH1_" because "UNIPHIER_" already
well specifies the SoC family. Also, rename files for consistency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/clk/clk-pro4.c')
| -rw-r--r-- | arch/arm/mach-uniphier/clk/clk-pro4.c | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c new file mode 100644 index 0000000..c784c31 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-pro4.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" +#include "../sc-regs.h" + +void ph1_pro4_clk_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | + SC_RSTCTRL_NRST_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_RSTCTRL_NRST_ETHER; +#endif +#ifdef CONFIG_USB_EHCI + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_RSTCTRL_NRST_NAND; +#endif + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp = readl(SC_RSTCTRL2); + tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; + writel(tmp, SC_RSTCTRL2); + readl(SC_RSTCTRL2); /* dummy read */ +#endif + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | + SC_CLKCTRL_CEN_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_CLKCTRL_CEN_ETHER; +#endif +#ifdef CONFIG_USB_EHCI + tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_CLKCTRL_CEN_NAND; +#endif + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} |