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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-02-05 10:52:12 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-02-23 08:37:56 +0900 |
| commit | 04cd4e7215d30431b736ef89c16d241c50a90c37 (patch) | |
| tree | b46fbd5ce22dac559d413253d5d60646f12d6dde /arch/arm/mach-uniphier/bcu | |
| parent | cf3175bcd8b21a87276016aceb9d7992a2151fca (diff) | |
| download | u-boot-imx-04cd4e7215d30431b736ef89c16d241c50a90c37.zip u-boot-imx-04cd4e7215d30431b736ef89c16d241c50a90c37.tar.gz u-boot-imx-04cd4e7215d30431b736ef89c16d241c50a90c37.tar.bz2 | |
ARM: uniphier: remove DRAM base address from board parameters
The base address of each DRAM channel can be calculated from other
parameters, so does not need hard-coding. What we need is the size
of each DRAM channel and DRAM_SPARSE flag to decide the start address
of DRAM channel 1.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/bcu')
| -rw-r--r-- | arch/arm/mach-uniphier/bcu/bcu-ld4.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/bcu/bcu-sld3.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-uniphier/bcu/bcu-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ld4.c index 7557880..a16b24e 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ld4.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ld4.c @@ -24,7 +24,7 @@ void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd) writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ /* Specify DDR channel */ - shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4; + shift = bd->dram_ch[0].size / 0x04000000 * 4; writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ shift -= 32; diff --git a/arch/arm/mach-uniphier/bcu/bcu-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-sld3.c index 64efd37..99b318f 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-sld3.c +++ b/arch/arm/mach-uniphier/bcu/bcu-sld3.c @@ -28,7 +28,7 @@ void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd) writel(0x24440000, BCSCR5); /* Specify DDR channel */ - shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4; + shift = bd->dram_ch[0].size / 0x04000000 * 4; writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ shift -= 32; |