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authorThierry Reding <treding@nvidia.com>2015-09-08 11:38:03 +0200
committerTom Warren <twarren@nvidia.com>2015-09-16 16:11:31 -0700
commitaba11d4476b56eb7712184597eb303ae544f0c69 (patch)
treee9b32cefb1b3a59f06b14fd3b522997dc3bf8ee9 /arch/arm/mach-tegra
parent20613c9231d53720b35ebe8ae67a9d4cf70a3620 (diff)
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ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/tegra124/clock.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index aa046e8..1e71146 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -809,6 +809,11 @@ void clock_early_init(void)
tegra30_set_up_pllp();
+ /* clear IDDQ before accessing any other PLLC registers */
+ pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
+ clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
+ udelay(2);
+
/*
* PLLC output frequency set to 600Mhz
* PLLD output frequency set to 925Mhz