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author | Minkyu Kang <mk7.kang@samsung.com> | 2015-11-20 15:24:57 +0900 |
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committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-11-30 17:17:01 +0900 |
commit | 225f5eeccd6c0d376a20c15897edd8c69500d8cc (patch) | |
tree | f1348e316a9c4b871d3cadbab9d9cdbe7ce5852a /arch/arm/mach-s5pc1xx/include/mach/sromc.h | |
parent | fa8883a1e39a20e72aaa5093af0c80062cb95757 (diff) | |
download | u-boot-imx-225f5eeccd6c0d376a20c15897edd8c69500d8cc.zip u-boot-imx-225f5eeccd6c0d376a20c15897edd8c69500d8cc.tar.gz u-boot-imx-225f5eeccd6c0d376a20c15897edd8c69500d8cc.tar.bz2 |
arm: s5pc1xx: move SoC to mach-s5pc1xx
move arm/arm/cpu/armv7/s5pc1xx to arch/arm/mach-s5pc1xx
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pc1xx/include/mach/sromc.h')
-rw-r--r-- | arch/arm/mach-s5pc1xx/include/mach/sromc.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pc1xx/include/mach/sromc.h b/arch/arm/mach-s5pc1xx/include/mach/sromc.h new file mode 100644 index 0000000..df1bf51 --- /dev/null +++ b/arch/arm/mach-s5pc1xx/include/mach/sromc.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Note: This file contains the register description for Memory subsystem + * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. + * + * Only SROMC is defined as of now + */ + +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ + +#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ +#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ +#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ +#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ +#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ +#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ +#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5p_sromc { + unsigned int bw; + unsigned int bc[6]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); + +#endif /* __ASM_ARCH_SMC_H_ */ |