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| author | Tom Rini <trini@konsulko.com> | 2016-12-12 07:19:28 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-12-12 07:19:28 -0500 |
| commit | b591730c357fd9347c4134ac2883ae039b79915c (patch) | |
| tree | f83d35d58b178dea34fed7dd71352e1aaa4eefb9 /arch/arm/mach-mvebu | |
| parent | fe9822556e051e6c24a3832532166ade00a81a8c (diff) | |
| parent | a20b7a2a53d3ac668d1ed25b06cd6d15ca41f2a9 (diff) | |
| download | u-boot-imx-b591730c357fd9347c4134ac2883ae039b79915c.zip u-boot-imx-b591730c357fd9347c4134ac2883ae039b79915c.tar.gz u-boot-imx-b591730c357fd9347c4134ac2883ae039b79915c.tar.bz2 | |
Merge git://www.denx.de/git/u-boot-marvell
Diffstat (limited to 'arch/arm/mach-mvebu')
| -rw-r--r-- | arch/arm/mach-mvebu/armada8k/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/armada8k/cache_llc.S | 39 |
2 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/armada8k/Makefile b/arch/arm/mach-mvebu/armada8k/Makefile index 84c69d9..0facf14 100644 --- a/arch/arm/mach-mvebu/armada8k/Makefile +++ b/arch/arm/mach-mvebu/armada8k/Makefile @@ -5,3 +5,4 @@ # obj-y = cpu.o +obj-y += cache_llc.o diff --git a/arch/arm/mach-mvebu/armada8k/cache_llc.S b/arch/arm/mach-mvebu/armada8k/cache_llc.S new file mode 100644 index 0000000..71aecb2 --- /dev/null +++ b/arch/arm/mach-mvebu/armada8k/cache_llc.S @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + * https://spdx.org/licenses + */ + +#include <asm/arch-armada8k/cache_llc.h> +#include <linux/linkage.h> + +/* + * int __asm_flush_l3_dcache + * + * flush Armada-8K last level cache. + * + */ +ENTRY(__asm_flush_l3_dcache) + /* flush cache */ + mov x0, #LLC_BASE_ADDR + add x0, x0, #LLC_FLUSH_BY_WAY + movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16 + mov w1, #LLC_WAY_MASK + str w1, [x0] + /* sync cache */ + mov x0, #LLC_BASE_ADDR + add x0, x0, #LLC_CACHE_SYNC + movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16 + str wzr, [x0] + /* check that cache sync completed */ + mov x0, #LLC_BASE_ADDR + add x0, x0, #LLC_CACHE_SYNC_COMPLETE + movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16 +1: ldr w1, [x0] + and w1, w1, #LLC_CACHE_SYNC_MASK + cbnz w1, 1b + /* return success */ + mov x0, #0 + ret +ENDPROC(__asm_flush_l3_dcache) |