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| author | Stefan Roese <sr@denx.de> | 2016-01-07 14:03:11 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-01-14 14:08:59 +0100 |
| commit | d35831f6fedbdfb0ce49814a225e854e5fa83c99 (patch) | |
| tree | 60f9d8293e9dc5a7461d89836738a46a0cbc4c7a /arch/arm/mach-mvebu/include | |
| parent | b7ca2501892887583de7d921e8dc332fc8d67f2f (diff) | |
| download | u-boot-imx-d35831f6fedbdfb0ce49814a225e854e5fa83c99.zip u-boot-imx-d35831f6fedbdfb0ce49814a225e854e5fa83c99.tar.gz u-boot-imx-d35831f6fedbdfb0ce49814a225e854e5fa83c99.tar.bz2 | |
arm: mvebu: Move SAR register defines into header
This is preparation for the runtime bootmode detection in spl.c.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Diffstat (limited to 'arch/arm/mach-mvebu/include')
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/soc.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 5d4ad30..f2cbd71 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -96,4 +96,25 @@ #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE +#if defined(CONFIG_ARMADA_38X) +/* SAR values for Armada 38x */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) +#define SAR_CPU_FREQ_OFFS 10 +#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 4 +#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS) +#else +/* SAR values for Armada XP */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) +#define SAR_CPU_FREQ_OFFS 21 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_FFC_FREQ_OFFS 24 +#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) +#define SAR2_CPU_FREQ_OFFS 20 +#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 5 +#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS) +#endif + #endif /* _MVEBU_SOC_H */ |