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| author | Stefano Babic <sbabic@denx.de> | 2015-10-23 12:35:42 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-10-23 12:35:42 +0200 |
| commit | a69fdc7787bfa2f27eed74c2ee58c28ce932d502 (patch) | |
| tree | 4731dbe1c7371c0c797641d9e755a93e614ec930 /arch/arm/mach-keystone/ddr3.c | |
| parent | 42e550d44bc2335a18065b155cc408f30f0502ef (diff) | |
| parent | 9f13b6d147dc74f2400ce18d9d4005ba53f21fd3 (diff) | |
| download | u-boot-imx-a69fdc7787bfa2f27eed74c2ee58c28ce932d502.zip u-boot-imx-a69fdc7787bfa2f27eed74c2ee58c28ce932d502.tar.gz u-boot-imx-a69fdc7787bfa2f27eed74c2ee58c28ce932d502.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/arm/mach-keystone/ddr3.c')
| -rw-r--r-- | arch/arm/mach-keystone/ddr3.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index dfb27b5..34606f4 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -52,7 +52,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); - __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); + if (!cpu_is_k2g()) + __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); @@ -64,6 +65,15 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) ; + /* Disable ECC for K2G */ + if (cpu_is_k2g()) { + clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1); + clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1); + } + __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) ; |