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| author | Tom Rini <trini@konsulko.com> | 2016-08-01 18:54:53 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-08-05 07:23:57 -0400 |
| commit | a78cd8613204188991c192b8dae2de0aae3b1722 (patch) | |
| tree | 1f181c9cffd17bccde12060eb6465544890c5f51 /arch/arm/mach-exynos/include | |
| parent | 65fcba1251dcb1fc2c48966406145a69fee3a817 (diff) | |
| download | u-boot-imx-a78cd8613204188991c192b8dae2de0aae3b1722.zip u-boot-imx-a78cd8613204188991c192b8dae2de0aae3b1722.tar.gz u-boot-imx-a78cd8613204188991c192b8dae2de0aae3b1722.tar.bz2 | |
ARM: Rework and correct barrier definitions
As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions. This was causing a failure to
boot of the Linux kernel.
In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions. This however introduces another complexity. Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it. Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier. The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Sandy Patterson <apatterson@sightlogix.com>
Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reported-by: Sandy Patterson <apatterson@sightlogix.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-exynos/include')
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/system.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 3ffb296..2c94a6b 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -38,16 +38,6 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) /* - * Data Synchronization Barrier acts as a special kind of memory barrier. - * No instruction in program order after this instruction executes until - * this instruction completes. This instruction completes when: - * - All explicit memory accesses before this instruction complete. - * - All Cache, Branch predictor and TLB maintenance operations before - * this instruction complete. - */ -#define dsb() __asm__ __volatile__ ("dsb\n\t" : : ); - -/* * This instruction causes an event to be signaled to all cores * within a multiprocessor system. If SEV is implemented, * WFE must also be implemented. |